|Category||Logic => Bus Interface => Bus Oriented Circuits|
|Title||Bus Oriented Circuits|
|Description||Quad Futurebus Backplane Transceiver|
|Company||Philips Semiconductors (Acquired by NXP)|
|Datasheet||Download 74F3893 datasheet
Quad backplane transceiver Drives heavily loaded backplanes with equivalent load Futurebus drivers sink 100mA Reduced voltage swing (1 volt) produces less noise and
reduces power consumption High speed operation enhances performance of backplane buses and facilitates incident wave switching Compatible with IEEE 896 and IEEE 1194.1 Futurebus Standards Builtin precision bandgap (BG) reference provides accurate receiver thresholds and improved noise immunity Glitchfree power up/power down operation on all outputs impedances down to 10 ohms
much less for BTL, so is its receiver threshold region, therefore noise margins are excellent. BTL offers low power consumption, low ground bounce, EMI and crosstalk, low capacitive loading, superior noise margin and low propagation delays. This results in a high bandwidth, reliable backplane.DESCRIPTION
The 74F3893 has four TTL outputs (Rn) on the receiver side with a common receiver enable input (RE). It has four data inputs (Dn) which are also TTL. These data inputs are NANDed with the data enable input (DE). The four I/O pins (bus side) are futurebus compatible, sink a minimum of 100mA, and are designed to drive heavily loaded backplanes with load impedances as low as 10 ohms. All outputs are designed to be glitchfree during power up and down.TYPE TYPICAL PROPAGATION DELAY 3.0ns TYPICAL SUPPLY CURRENT( TOTAL) 55mA
The is a quad backplane transceivers and is intended to be used in very high speed bus systems. The 74F3893 interfaces to `Backplane Transceiver Logic' (BTL). BTL features a reduced to 2V) voltage swing for lower power consumption and a series diode on the drivers to reduce capacitive loading 5pF). Incident wave switching is employed, therefore BTL propagation delays are short. Although the voltage swing isDESCRIPTION ORDER CODE COMMERCIAL RANGE VCC 5V ±10%, Tamb +70°C N74F3893A PKG DWG #
PINS I/O3 Data inputs Data enable input Receiver enable input Bus inputs Bus outputs DESCRIPTION 74F (U.L.) HIGH/LOW OC/166.7 150/40 LOAD VALUE HIGH/LOW OC/100mA 3mA/24mA
R7 Receiver outputs Notes to input and output loading and fan out table One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state. OC= Open collector.
Notes to function table H = High voltage level L = Low voltage level X = Don't care Z = High impedance "off" state
|Some Part number from the same manufacture Philips Semiconductors (Acquired by NXP)|
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|74F395 4-bit Cascadable Shift Register (3-state)|
|74F399 74F399; Quad 2-port Register;; Package: SOT109 (SO16), SOT38-4 (DIP16)|
|74F40 74F40; Dual 4-input NAND Buffer|
|74F456 74F456; Octal Buffer/driver With Parity, Non-inverting (3-State);; Package: SOT137 (SO24), SOT222-1 (DIP24)|
|74F50109 74F50109; Synchronizing Dual J-k Positive Edge-triggered Flip-flop With Metastable Immune Characteristics;; Package: SOT109 (SO16), SOT38-4 (DIP16)|
|74F50728 74F50728; Synchronizing Cascaded Dual Positive Edge-triggered D-type Flip-flop;; Package: SOT108-1 (SO14), SOT27-1 (DIP14)|
|74F50729 74F50729; Synchronizing Dual D-type Flip-flop With Edge-triggered Set And Reset And Metastable Immune Characteristics;; Package: SOT27-1 (DIP14)|
|74F5074 74F5074; Synchronizing Dual D-type Flip-flop/clock Driver;; Package: SOT27-1 (DIP14)|
|74F51 74F51; Dual 2-wide 2-input, 2-wise 3-input And-or-invert Gate;; Package: SOT108-1 (SO14), SOT27-1 (DIP14)|
|74F521 74F521; 8-bit Identity Comparator;; Package: SOT146-1 (DIP20), SOT163 (SO20)|
|74F524 74F524; 8-bit Register Comparator (open-collector + 3-State);; Package: SOT146-1 (DIP20), SOT163 (SO20)|
|74F5300 74F5300; Fiber Optic Led Driver;; Package: SOT96 (SO8), SOT97-1 (DIP8)|
|74F5302 Fiber Optic Dual Led /clock Driver|
|74F534 74F534; Octal D Flip-flop, Inverting (3-State);; Package: SOT146-1 (DIP20), SOT163 (SO20)|
|74F537 74F537; 1-of-10 Decoder (3-State)|
|74F538 74F538; 1-of-8 Decoder (3-State);; Package: SOT146-1 (DIP20), SOT163 (SO20)|
|74F539 Dual 1-of-4 Decoder (3-state)|
|74F540 74F540; 74F541; Octal Inverter Buffer (3- State); Octal Buffer (3- State);; Package: SOT146-1 (DIP20), SOT163-1 (SO20)|
5962-9677301QRA : D-Type (3-State) Flip-Flops. ti CD54AC574, Non-inverting Octal D-type Flip-flops With 3-State Outputs.
74ACT11174DW : D-Type Flip-Flops. ti 74ACT11174, 6-Bit Positive-edge-triggered D-type Flip-flops With Clear.
CD4504B : CMOS/BiCMOS->4000 Family. CMOS Hex Voltage-level Shifter For Ttl-to-cmos or CMOS-to-cmos Operation.
DM54191J : Synchronous Up/down 4-bit Binary Counter With Mode Control. DM54191 DM74191 Synchronous Up Down 4-Bit Binary Counter with Mode Control DM54191 DM74191 Synchronous Up Down 4-Bit Binary Counter with Mode Control This circuit is a synchronous reversible up down counter The a 4-bit binary counter Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change simultaneously.
HEF4011B : HEF4011B; Quadruple 2-input NAND Gate;; Package: SOT108-1 (SO14), SOT27-1 (DIP14).
IS82C88 : CMOS Bus Controller. The Intersil is a high performance CMOS Bus Controller manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C88 provides the control and command timing signals for 80C86, 80C88, and 80188 based systems. The high output drive capability of the 82C88 eliminates the need for additional bus drivers. Static CMOS circuit design.
M74HCT161C1R : Synchronous Presettable 4-bit Counter. HIGH SPEED fMAX = 50 MHz (TYP.) AT VCC 5 V LOW POWER DISSIPATION ICC 4 µA (MAX.) 25 °C OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS BALANCED PROPAGATION DELAYS tPLH = tPHL SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL 4 mA (MIN.) COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.); VIL = 0.8V (MAX.) PIN AND FUNCTION COMPATIBLE WITH 54/74LS160 163 M54/74HCT160 Decade, Asynchronous.
MC100E175FN : 5V Ecl 9-Bit Latch With Parity , Package: Plcc, Pins=28. The a 9-bit latch. It also a tenth latched output, ODDPAR, which is formed as the odd parity of the nine data inputs (ODDPAR is HIGH if an odd number of the inputs are HIGH). The E175 can also be used to generate byte parity by using D8 as the parity-type select (L = even parity, H = odd parity), and using ODDPAR as the byte parity output. The LEN pin latches.
MC74HC08ADT : Quad 2-Input And Gate, Package: Tssop, Pins=14. The MC74HC08A is identical in pinout to the LS08. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: to 6V Low Input Current: 1µA High Noise Immunity Characteristic.
MC74VHC1GT32 : Single 2 Input OR GATE, TTL Level. The is an advanced high speed CMOS 2input OR gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The device.
OR4E4 : Field-programmable Gate Arrays. High-performance platform design. 0.13 µm seven-level metal technology. Internal performance of >250 MHz (four logic levels). I/O performance of >416 MHz for all user I/Os. Over 1.5 million usable system gates. Meets multiple I/O interface standards. 1.5 V operation (30% less power than 1.8 V operation) translates to greater performance. Embedded.
SN74LS151M : Multiplexers. 8-Input Multiplexer, Package: SOEIAJ-16, Pins=16. The TTL/MSI is a high speed 8-input Digital Multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. The LS151 can be used as a universal function generator to generate any logic function of four variables. Both assertion and negation outputs are provided. Schottky Process for High Speed Multifunction.
SN74LS253D : Multiplexers. ti SN74LS253, Dual 4-Line to 1-Line Data Selectors/multiplexers With 3-State Outputs.
74AUP2G79GD : AUP/ULP/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO8. s: Flip-Flop Type: D ; Triggering: Positive-edge Triggered ; Supply Voltage: 1.1 ; Output Characteristics: TRUE ; Propagation Delay: 25.6 ns ; fMAX: 510 MHz ; Operating Temperature: -40 to 125 C (-40 to 257 F) ; Package Type: 3 X 2 MM, 0.50 MM HEIGHT, PLASTIC, SOT996-2,.