Details, datasheet, quote on part number: 74F3893
Part74F3893
CategoryLogic => Bus Interface => Bus Oriented Circuits
TitleBus Oriented Circuits
DescriptionQuad Futurebus Backplane Transceiver
CompanyPhilips Semiconductors (Acquired by NXP)
DatasheetDownload 74F3893 datasheet
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Features, Applications

FEATURES

Quad backplane transceiver Drives heavily loaded backplanes with equivalent load Futurebus drivers sink 100mA Reduced voltage swing (1 volt) produces less noise and

reduces power consumption High speed operation enhances performance of backplane buses and facilitates incident wave switching Compatible with IEEE 896 and IEEE 1194.1 Futurebus Standards Built­in precision band­gap (BG) reference provides accurate receiver thresholds and improved noise immunity Glitch­free power up/power down operation on all outputs impedances down to 10 ohms

much less for BTL, so is its receiver threshold region, therefore noise margins are excellent. BTL offers low power consumption, low ground bounce, EMI and crosstalk, low capacitive loading, superior noise margin and low propagation delays. This results in a high bandwidth, reliable backplane.

DESCRIPTION

The 74F3893 has four TTL outputs (Rn) on the receiver side with a common receiver enable input (RE). It has four data inputs (Dn) which are also TTL. These data inputs are NANDed with the data enable input (DE). The four I/O pins (bus side) are futurebus compatible, sink a minimum of 100mA, and are designed to drive heavily loaded backplanes with load impedances as low as 10 ohms. All outputs are designed to be glitch­free during power up and down.

TYPE TYPICAL PROPAGATION DELAY 3.0ns TYPICAL SUPPLY CURRENT( TOTAL) 55mA

The is a quad backplane transceivers and is intended to be used in very high speed bus systems. The 74F3893 interfaces to `Backplane Transceiver Logic' (BTL). BTL features a reduced to 2V) voltage swing for lower power consumption and a series diode on the drivers to reduce capacitive loading 5pF). Incident wave switching is employed, therefore BTL propagation delays are short. Although the voltage swing is

DESCRIPTION ORDER CODE COMMERCIAL RANGE VCC 5V ±10%, Tamb +70°C N74F3893A PKG DWG #

PINS ­ I/O3 Data inputs Data enable input Receiver enable input Bus inputs Bus outputs DESCRIPTION 74F (U.L.) HIGH/LOW OC/166.7 150/40 LOAD VALUE HIGH/LOW OC/100mA 3mA/24mA

­ R7 Receiver outputs Notes to input and output loading and fan out table One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state. OC= Open collector.

Notes to function table H = High voltage level L = Low voltage level X = Don't care Z = High impedance "off" state


 

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