|Category||Logic => Registers => Bipolar->F Family|
|Description||4-bit Cascadable Shift Register (3-state)|
|Company||Philips Semiconductors (Acquired by NXP)|
|Datasheet||Download 74F395 datasheet
4-bit parallel load shift register Independent 3-State buffer outputs, Q0Q3 Separate Qs output for serial expansion Asynchronous Master ResetDESCRIPTION
The a 4-bit Shift Register with serial and parallel synchronous operating modes and 3-State buffer outputs. The shifting and loading operations are controlled by the state of the Parallel Enable (PE) input. When PE is High, data is loaded from the Parallel Data inputs (D0D3) into the register synchronous with the High-to-Low transition of the Clock input (CP). When PE is Low, the data at the Serial Data input (Ds) is loaded into the Q0 flip-flop, and the data in the register is shifted one bit to the right in the direction (Q0!Q1!Q2!Q3) synchronous with the negative clock transition. The PE and Data inputs are fully edge-triggered and must be stable one setup prior to the High-to-Low transition of the clock. The Master Reset (MR) is an asynchronous active-Low input. When Low, the MR overrides the clock and all other inputs and clears the register. The 3-state output buffers are designed to drive heavily loaded 3-State buses, or large capacitive loads. The active-Low Output Enable (OE) controls all four 3-State buffers independent of the register operation. The data in the register appears at the outputs when OE is Low. The outputs are in High impedance "OFF" state, which means they will neither drive nor load the bus when OE is High. The output from the last stage is brought out separately. This output (Qs) is tied to the Serial Data input (Ds) of the next register for serial expansion applications. The Qs output is not affected by the 3-State buffer operation.
DESCRIPTION 16-pin plastic DIP 16-pin plastic SO COMMERCIAL RANGE VCC 5V ±10%, Tamb N74F395N N74F395D
PINS Qs Q0Q3 Data inputs Serial data input Parallel Enable input Master Reset input (active Low) Output Enable input (active Low) Clock Pulse input (active falling edge) Serial expansion output Data outputs (3-State) DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW 1.0mA/20mA 3.0mA/24mANOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
INPUTS Dn Q0 OUTPUTS L q2 Shift right q2 L Parallel load H 3-STATE BUFFER OPERATING MODES Read Disable buffers H REGISTER OPERATING MODES Reset (clear) H = High voltage level h = High voltage level one set-up time prior to the High-to-Low clock transition L = Low voltage level l = Low voltage level one set-up time prior to the High-to-Low clock transition qn = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the High-to-Low clock transition X = Don't care Z = High impedance "OFF" state # = High-to-Low clock transition
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Qs Current applied to output in Low output state Q0Q3 Operating free-air temperature range Storage temperature range mA °C PARAMETER RATING +5.5 40 UNIT V mA
LIMITS SYMBOL VCC VIH VIL IIK IOH Supply voltage High-level input voltage Low-level input voltage Input clamp current Qs High-level output current Q0Q3 Qs IOL Tamb Low-level output current Q0Q3 Operating free-air temperature range 20 mA PARAMETER MIN NOM 5.0 MAX V mA UNIT
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