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Details, datasheet, quote on part number: 74F40
CategoryLogic => Gates => Bipolar->F Family
TitleBipolar->F Family
Description74F40; Dual 4-input NAND Buffer
CompanyPhilips Semiconductors (Acquired by NXP)
DatasheetDownload 74F40 datasheet
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Features, Applications

DESCRIPTION 14-pin plastic DIP 14-pin plastic SO COMMERCIAL RANGE VCC 5V 10%, Tamb N74F40N N74F40D

PINS Dna, Dnb, Dnc, Dnd Q0, Q1 Data inputs Data outputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/2.0 750/106.7 LOAD VALUE HIGH/LOW 20A/1.2mA 15mA/64mA

NOTE: One (1.0) FAST unit load is defined as: 20A in the High state and 0.6mA in the Low state.
H NOTES: H = High voltage level L = Low voltage level X = Don't care

(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature range PARAMETER RATING 0.5 to VCC to +150 UNIT mA C

LIMITS SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARAMETER MIN NOM 5.0 MAX mA C UNIT

(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST 0.42 0.73 LIMITS MIN V VIN = GND VIN V TYP2 MAX UNIT

Low-level output voltage Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Short-circuit output current3 Supply current (total) ICCH ICCL

NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.

LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5.0V Tamb = 500 MIN tPLH tPHL Propagation delay Dna, Dnb, Dnc, Dnd to Qn Waveform 2.0 1.5 TYP 4.0 3.0 MAX 6.0 5.0 VCC 10% Tamb = 500 MIN 1.5 1.0 MAX 5.5 ns UNIT

Waveform 1. Propagation Delay for Inverting Outputs NOTE: For all waveforms, = 1.5V.


Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators.

Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude 3.0V 1.5V rep. rate tw 500ns tTLH 2.5ns tTHL 2.5ns


Some Part number from the same manufacture Philips Semiconductors (Acquired by NXP)
74F455 Buffers/drivers
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74F50109 74F50109; Synchronizing Dual J-k Positive Edge-triggered Flip-flop With Metastable Immune Characteristics;; Package: SOT109 (SO16), SOT38-4 (DIP16)
74F50728 74F50728; Synchronizing Cascaded Dual Positive Edge-triggered D-type Flip-flop;; Package: SOT108-1 (SO14), SOT27-1 (DIP14)
74F50729 74F50729; Synchronizing Dual D-type Flip-flop With Edge-triggered Set And Reset And Metastable Immune Characteristics;; Package: SOT27-1 (DIP14)
74F5074 74F5074; Synchronizing Dual D-type Flip-flop/clock Driver;; Package: SOT27-1 (DIP14)
74F51 74F51; Dual 2-wide 2-input, 2-wise 3-input And-or-invert Gate;; Package: SOT108-1 (SO14), SOT27-1 (DIP14)
74F521 74F521; 8-bit Identity Comparator;; Package: SOT146-1 (DIP20), SOT163 (SO20)
74F524 74F524; 8-bit Register Comparator (open-collector + 3-State);; Package: SOT146-1 (DIP20), SOT163 (SO20)
74F5300 74F5300; Fiber Optic Led Driver;; Package: SOT96 (SO8), SOT97-1 (DIP8)
74F5302 Fiber Optic Dual Led /clock Driver
74F534 74F534; Octal D Flip-flop, Inverting (3-State);; Package: SOT146-1 (DIP20), SOT163 (SO20)
74F537 74F537; 1-of-10 Decoder (3-State)
74F538 74F538; 1-of-8 Decoder (3-State);; Package: SOT146-1 (DIP20), SOT163 (SO20)
74F539 Dual 1-of-4 Decoder (3-state)
74F540 74F540; 74F541; Octal Inverter Buffer (3- State); Octal Buffer (3- State);; Package: SOT146-1 (DIP20), SOT163-1 (SO20)
74F543 74F543; 74F544; Octal Registered Transceiver, Non-inverting (3-State); Octal Registered Transceiver,inverting (3-State);; Package: SOT137 (SO24), SOT222-1 (DIP24), SOT340-1 (SSOP24)
74F545 74F545; Octal Bidirectional Transceiver (with 3-State Inputs/outputs);; Package: SOT146-1 (DIP20), SOT163 (SO20)
74F552 74F552; Octal Registered Transceiver With Parity And Flags (3-State);; Package: SOT117-1 (DIP28), SOT136-1 (SO28)
74F564 74F564; Octal D Flip-flop (3-State);; Package: SOT146-1 (DIP20), SOT163-1 (SO20)
74F569 74F569; 4-bit Bidirectional Binary Synchronous Counter (3-State)
0-C     D-L     M-R     S-Z