|Category||Logic => Gates => Bipolar->F Family|
|Description||74F40; Dual 4-input NAND Buffer|
|Company||Philips Semiconductors (Acquired by NXP)|
|Datasheet||Download 74F40 datasheet
DESCRIPTION 14-pin plastic DIP 14-pin plastic SO COMMERCIAL RANGE VCC 5V ±10%, Tamb N74F40N N74F40D
PINS Dna, Dnb, Dnc, Dnd Q0, Q1 Data inputs Data outputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/2.0 750/106.7 LOAD VALUE HIGH/LOW 20µA/1.2mA 15mA/64mANOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
H NOTES: H = High voltage level L = Low voltage level X = Don't care
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature range PARAMETER RATING 0.5 to VCC to +150 UNIT mA °C
LIMITS SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARAMETER MIN NOM 5.0 MAX mA °C UNIT
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST 0.42 0.73 LIMITS MIN V VIN = GND VIN V TYP2 MAX UNIT
Low-level output voltage Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Short-circuit output current3 Supply current (total) ICCH ICCL
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5.0V Tamb = 500 MIN tPLH tPHL Propagation delay Dna, Dnb, Dnc, Dnd to Qn Waveform 2.0 1.5 TYP 4.0 3.0 MAX 6.0 5.0 VCC ± 10% Tamb = 500 MIN 1.5 1.0 MAX 5.5 ns UNITWaveform 1. Propagation Delay for Inverting Outputs NOTE: For all waveforms, = 1.5V.
VCC NEGATIVE PULSE VIN PULSE GENERATOR RT D.U.T. VOUT VM 10% tTHL (tf VM 10% tTLH (tr 0V 90% AMP (V)
Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude 3.0V 1.5V rep. rate tw 500ns tTLH 2.5ns tTHL 2.5ns
|Some Part number from the same manufacture Philips Semiconductors (Acquired by NXP)|
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