74F50109 Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics
Synchronizing dual JK positive edge-triggered flip-flop with metastable immune characteristics
· Metastable immune characteristics· Output skew guaranteed less than 1.5ns· High source current (IOH = 15mA) ideal for clock driver
· Pinout compatible with 74F109· See 74F5074 for synchronizing dual D-type flip-flop· See 74F50728 for synchronizing cascaded D-type flip-flop· See 74F50729 for synchronizing dual D-type flip-flop with
edge-triggered set and reset TYPE 74F50109 TYPICAL fmax 150MHz TYPICAL SUPPLY CURRENT( TOTAL) 22mA
ORDER CODE COMMERCIAL RANGE DESCRIPTION Tamb +70°C 16pin plastic DIP 16pin plastic SOT38-4 SOT109-1 VCC 5V ±10%, PKG DWG #
PINS RD0, RD1 DESCRIPTION J inputs K inputs Clock inputs (active rising edge) Set inputs (active low) Reset inputs (active low) 74F (U.L.) HIGH/ LOW LOAD VALUE HIGH/LOW 20µA/250µA 20µA/20µA
Q0, Q1 Data outputs 750/33 15mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
deviceundertest can be often be driven into a metastable state. If the Q output is then used to trigger a digital scope set to infinite persistence the Q output will build waveform.0 An experiment was run by continuously operating the devices in the region where metastability will occur. When the deviceundertest a 74F74 (which was not designed with metastable immune characteristics) the waveform will appear as in Fig. 2.
Fig. 2 shows clearly that the Q output can vary in time with respect to the Q trigger point. This also implies that the or Q output waveshapes may be distorted. This can be verified on an analog scope with a charge plate CRT. Perhaps of even greater interest are the dots running along the 3.5V volt line in the upper right hand quadrant. These show that the Q output did not change state even though the Q output glitched to at least 1.5 volts, the trigger point of the scope. When the deviceundertest is a metastable immune part, such as the 74F5074, the waveform will appear as in Fig. 3. The 74F5074 Q output will appear as in Fig. 3. The 74F5074 Q output will not vary with respect to the Q trigger point even when the a part is driven into a metastable state. Any tendency towards internal metastability is resolved by Philips Semiconductors patented circuitry. If a metastable event occurs within the flop the only outward manifestation of the event will be an increased clocktoQ/Q propagation delay. This propagation delay is, of course, a function of the metastability characteristics of the part defined by and T0. The metastability characteristics of the 74F5074 and related part types represent stateoftheart TTL technology. After determining the T0 and t of the flop, calculating the mean time between failures (MTBF) is simple. Suppose a designer wants to use the 74F50729 for synchronizing asynchronous data that is arriving at 10MHz (as measured by a frequency counter), has a clock frequency of 50MHz, and has decided that he would like to sample the output of the 74F50109 10 nanoseconds after the clock edge. He simply plugs his number into the equation below: MTBF = e(t'/t)/ TofCfI In this formula, fC is the frequency of the clock, fI is the average input event frequency, and t' is the time after the clock pulse that the output is sampled (t' h, h being the normal propagation delay). In this situation the fI will be twice the data frequency of 20 MHz because input events consist of both of low and high transitions. Multiplying by fC gives an answer 1015 Hz2. From Fig. it is clear that the MTBF is greater than 1010 seconds. Using the above formula MTBF X 1010 seconds or about 480 years.
The is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock (CP) input. The J and K are edgetriggered inputs which control the state changes of the flipflops as described in the function table. The J and K inputs must be stable just one setup time prior to the lowtohigh transition of the clock for guaranteed propagation delays. The JK design allows operation a D flipflop by tying J and K inputs together. The 74F50109 is designed so that the outputs can never display a metastable state due to setup and hold time violations. If setup time and hold time are violated the propagation delays may be extended beyond the specifications but the outputs will not glitch or display a metastable state. Typical metastability parameters for the 74F50109 are: 135ps and X 106 sec where represents a function of the rate at which a latch in a metastable state resolves that condition and T0 represents a function of the measurement of the propensity of a latch to enter a metastable state.
Philips Semiconductors uses the term 'metastable immune' to describe characteristics of some of the products in its FAST family. Specifically the 74F50XXX family presently consist of 4 products which displays metastable immune characteristics. This term means that the outputs will not glitch or display an output anomaly under any circumstances including setup and hold time violations. This claim is easily verified on the 74F5074. By running two independent signal generators (see Fig. 1) at nearly the same frequency (in this case 10MHz clock and 10.02 MHz data) the
SIGNAL GENERATOR D Q TRIGGER DIGITAL SCOPE SIGNAL GENERATOR CP Q INPUT