Details, datasheet, quote on part number: 74F50109
Part74F50109
CategoryLogic => Flip-Flops
Description74F50109; Synchronizing Dual J-k Positive Edge-triggered Flip-flop With Metastable Immune Characteristics;; Package: SOT109 (SO16), SOT38-4 (DIP16)
CompanyPhilips Semiconductors (Acquired by NXP)
DatasheetDownload 74F50109 datasheet
Quote
Find where to buy
 
  

 

Features, Applications

74F50109 Synchronizing dual J-K positive edge-triggered flip-flop with metastable immune characteristics

Synchronizing dual J­K positive edge-triggered flip-flop with metastable immune characteristics
FEATURE

Metastable immune characteristics Output skew guaranteed less than 1.5ns High source current (IOH = 15mA) ideal for clock driver

applications

Pinout compatible with 74F109 See 74F5074 for synchronizing dual D-type flip-flop See 74F50728 for synchronizing cascaded D-type flip-flop See 74F50729 for synchronizing dual D-type flip-flop with

edge-triggered set and reset TYPE 74F50109 TYPICAL fmax 150MHz TYPICAL SUPPLY CURRENT( TOTAL) 22mA

ORDER CODE COMMERCIAL RANGE DESCRIPTION Tamb +70°C 16­pin plastic DIP 16­pin plastic SOT38-4 SOT109-1 VCC 5V ±10%, PKG DWG #

PINS RD0, RD1 DESCRIPTION J inputs K inputs Clock inputs (active rising edge) Set inputs (active low) Reset inputs (active low) 74F (U.L.) HIGH/ LOW LOAD VALUE HIGH/LOW 20µA/250µA 20µA/20µA

Q0, Q1 Data outputs 750/33 15mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.

device­under­test can be often be driven into a metastable state. If the Q output is then used to trigger a digital scope set to infinite persistence the Q output will build waveform.0 An experiment was run by continuously operating the devices in the region where metastability will occur. When the device­under­test a 74F74 (which was not designed with metastable immune characteristics) the waveform will appear as in Fig. 2.

Fig. 2 shows clearly that the Q output can vary in time with respect to the Q trigger point. This also implies that the or Q output waveshapes may be distorted. This can be verified on an analog scope with a charge plate CRT. Perhaps of even greater interest are the dots running along the 3.5V volt line in the upper right hand quadrant. These show that the Q output did not change state even though the Q output glitched to at least 1.5 volts, the trigger point of the scope. When the device­under­test is a metastable immune part, such as the 74F5074, the waveform will appear as in Fig. 3. The 74F5074 Q output will appear as in Fig. 3. The 74F5074 Q output will not vary with respect to the Q trigger point even when the a part is driven into a metastable state. Any tendency towards internal metastability is resolved by Philips Semiconductors patented circuitry. If a metastable event occurs within the flop the only outward manifestation of the event will be an increased clock­to­Q/Q propagation delay. This propagation delay is, of course, a function of the metastability characteristics of the part defined by and T0. The metastability characteristics of the 74F5074 and related part types represent state­of­the­art TTL technology. After determining the T0 and t of the flop, calculating the mean time between failures (MTBF) is simple. Suppose a designer wants to use the 74F50729 for synchronizing asynchronous data that is arriving at 10MHz (as measured by a frequency counter), has a clock frequency of 50MHz, and has decided that he would like to sample the output of the 74F50109 10 nanoseconds after the clock edge. He simply plugs his number into the equation below: MTBF = e(t'/t)/ TofCfI In this formula, fC is the frequency of the clock, fI is the average input event frequency, and t' is the time after the clock pulse that the output is sampled (t' h, h being the normal propagation delay). In this situation the fI will be twice the data frequency of 20 MHz because input events consist of both of low and high transitions. Multiplying by fC gives an answer 1015 Hz2. From Fig. it is clear that the MTBF is greater than 1010 seconds. Using the above formula MTBF X 1010 seconds or about 480 years.

DESCRIPTION

The is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock (CP) input. The J and K are edge­triggered inputs which control the state changes of the flip­flops as described in the function table. The J and K inputs must be stable just one setup time prior to the low­to­high transition of the clock for guaranteed propagation delays. The JK design allows operation a D flip­flop by tying J and K inputs together. The 74F50109 is designed so that the outputs can never display a metastable state due to setup and hold time violations. If setup time and hold time are violated the propagation delays may be extended beyond the specifications but the outputs will not glitch or display a metastable state. Typical metastability parameters for the 74F50109 are: 135ps and X 106 sec where represents a function of the rate at which a latch in a metastable state resolves that condition and T0 represents a function of the measurement of the propensity of a latch to enter a metastable state.

Philips Semiconductors uses the term 'metastable immune' to describe characteristics of some of the products in its FAST family. Specifically the 74F50XXX family presently consist of 4 products which displays metastable immune characteristics. This term means that the outputs will not glitch or display an output anomaly under any circumstances including setup and hold time violations. This claim is easily verified on the 74F5074. By running two independent signal generators (see Fig. 1) at nearly the same frequency (in this case 10MHz clock and 10.02 MHz data) the

SIGNAL GENERATOR D Q TRIGGER DIGITAL SCOPE SIGNAL GENERATOR CP Q INPUT

 

Some Part number from the same manufacture Philips Semiconductors (Acquired by NXP)
74F50728 74F50728; Synchronizing Cascaded Dual Positive Edge-triggered D-type Flip-flop;; Package: SOT108-1 (SO14), SOT27-1 (DIP14)
74F50729 74F50729; Synchronizing Dual D-type Flip-flop With Edge-triggered Set And Reset And Metastable Immune Characteristics;; Package: SOT27-1 (DIP14)
74F5074 74F5074; Synchronizing Dual D-type Flip-flop/clock Driver;; Package: SOT27-1 (DIP14)
74F51 74F51; Dual 2-wide 2-input, 2-wise 3-input And-or-invert Gate;; Package: SOT108-1 (SO14), SOT27-1 (DIP14)
74F521 74F521; 8-bit Identity Comparator;; Package: SOT146-1 (DIP20), SOT163 (SO20)
74F524 74F524; 8-bit Register Comparator (open-collector + 3-State);; Package: SOT146-1 (DIP20), SOT163 (SO20)
74F5300 74F5300; Fiber Optic Led Driver;; Package: SOT96 (SO8), SOT97-1 (DIP8)
74F5302 Fiber Optic Dual Led /clock Driver
74F534 74F534; Octal D Flip-flop, Inverting (3-State);; Package: SOT146-1 (DIP20), SOT163 (SO20)
74F537 74F537; 1-of-10 Decoder (3-State)
74F538 74F538; 1-of-8 Decoder (3-State);; Package: SOT146-1 (DIP20), SOT163 (SO20)
74F539 Dual 1-of-4 Decoder (3-state)
74F540 74F540; 74F541; Octal Inverter Buffer (3- State); Octal Buffer (3- State);; Package: SOT146-1 (DIP20), SOT163-1 (SO20)
74F543 74F543; 74F544; Octal Registered Transceiver, Non-inverting (3-State); Octal Registered Transceiver,inverting (3-State);; Package: SOT137 (SO24), SOT222-1 (DIP24), SOT340-1 (SSOP24)
74F545 74F545; Octal Bidirectional Transceiver (with 3-State Inputs/outputs);; Package: SOT146-1 (DIP20), SOT163 (SO20)
74F552 74F552; Octal Registered Transceiver With Parity And Flags (3-State);; Package: SOT117-1 (DIP28), SOT136-1 (SO28)
74F564 74F564; Octal D Flip-flop (3-State);; Package: SOT146-1 (DIP20), SOT163-1 (SO20)
74F569 74F569; 4-bit Bidirectional Binary Synchronous Counter (3-State)
74F573 74F573; 74F574; Octal Transparent Latch (3-State); Octal Transparent Latch (3-State);; Package: SOT146-1 (DIP20), SOT163 (SO20), SOT339-1 (SSOP20)
74F579 74F579; 8-bit Bidirectional Binary Counter (3-State);; Package: SOT146-1 (DIP20), SOT163 (SO20)
74F583 74F583; 4-bit BCD Adder;; Package: SOT162-1 (SO16), SOT38-1 (DIP16)
Same catergory

54AC821F : 10-bit D Flip-flop With Tri-state Outputs. The 10-bit D flip-flop with TRI-STATE outputs arranged in a broadside pinout. The 'AC/'ACT821 is functionally identical to the AM29821. Noninverting outputs Outputs source/sink mA 'ACT821 has TTL-compatible inputs Standard Microcircuit Drawing (SMD) 'AC821: 5962-91606 Data Inputs Data Outputs Output Enable Input Clock Input TRI-STATE is a registered.

74ACT257 : CMOS/BiCMOS->AC/ACT Family->Advanced High Speed CM. Quad 2 Channel Multiplexer (3-STATE).

74F569 : Bipolar->F Family. 74F569; 4-bit Bidirectional Binary Synchronous Counter (3-State).

74LV165 : 74LV165; 8-bit Parallel-in/serial-out Shift Register;; Package: SOT109 (SO16), SOT338-1 (SSOP16), SOT38-4 (DIP16), SOT403-1 (TSSOP16).

CD54HC85 : CMOS/BiCMOS->HC/HCT Family. High Speed CMOS Logic 4-bit Magnitude Comparator.

DM74ALS137 : Bipolar->ALS Family. 3-Line to 8-Line Decoder/demultiplexer With Address Latches.

SN54ABT162601 : Bus Oriented Circuits. Members of the Texas Instruments Widebus TM Family B-Port Outputs Have Equivalent 25- Series Resistors, So No External Resistors Are Required State-of-the-Art EPIC-B TM BiCMOS Design Significantly Reduces Power Dissipation UBT TM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked,.

SN74ALS642A-1 : Bus Oriented Circuits. Bidirectional Bus Transceivers in High-Density 20-Pin Packages Choice of True or Inverting Logic Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (N) 300-mil DIPs These octal bus transceivers are designed for asynchronous two-way communication between data buses. These devices transmit data from the A bus to the B bus or from.

SN74CB3T3245DBQR : Standard Bus Switches. ti SN74CB3T3245, 8-Bit Fet 2.5-V/3.3-V Low-voltage Bus Switch With 5-V Tolerant Level Shifter.

SN74LVC1G66 : . Available in the Texas Instruments NanoStar and NanoFree Packages to 5.5-V VCC Operation Inputs Accept Voltages 5.5 V Max tpd 3.3 V High On-Off Output Voltage Ratio High Degree of Linearity High Speed, Typically 0.5 ns (VCC = 50 pF) Low On-State Resistance, Typically 5.5 (VCC 4.5 V) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection.

TC74HC697 : Synchronous Counters-> CMOS/BiCMOS->HC/HCT Family. Sychronous Presettable 4-bit Binary Up/down Counter With Output Register (multiplexed 3-state Outputs).

UC1877 : Phase Shift Resonant Controller. Zero to 100% Duty Cycle Control Programmable Output Turn-On Delay Compatible with Voltage or Current Mode Topologies Practical Operation at Switching Frequencies to 1MHz Four 2A Totem Pole Outputs 10MHz Error Amplifier Undervoltage Lockout Low Startup Current ­150µA Outputs Active Low During UVLO Soft-Start Control Latched Over-Current Comparator With.

SN74AVC1T45 : Single-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation and 3-State Outputs This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVC1T45 is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. It is operational with VCCA/VCCB as low as 1.2 V. The A-port is designed to track.

AM4055DC : 4000/14000/40000 SERIES, 128-BIT RIGHT SERIAL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16. s: Register Type: Serial In / Serial Out - Shift Right ; Shift Direction: Right ; Supply Voltage: 5V ; Package Type: DIP, Other, HERMETIC SEALED, SIDE BRAZED, DIP-16 ; Logic Family: CMOS ; Pin Count: 16 ; Number of units in IC: 4 ; Number of Bits (Stages):.

NLV37WZ07USG : LVC/LCX/Z SERIES, TRIPLE 1-INPUT NON-INVERT GATE, PDSO8. s: Gate Type: NON-INVERT ; Supply Voltage: 1.8V ; Output Type: Open Drain ; Inputs: 1 ; Propagation Delay: 7.8 ns ; Operating Temperature: -55 to 125 C (-67 to 257 F) ; Pin Count: 8 ; IC Package Type: Other, ROHS COMPLIANT, US-8.

TC4S69F(TE12L) : 4000/14000/40000 SERIES, 1-INPUT INVERT GATE, PDSO5. s: Gate Type: NOT ; Supply Voltage: 5V ; Logic Family: CMOS ; Inputs: 1 ; Propagation Delay: 200 ns ; Operating Temperature: -40 to 85 C (-40 to 185 F) ; Pin Count: 5 ; IC Package Type: SSOP, Other, PLASTIC, SSOP-5.

TC7W74FKTE12L : HC/UH SERIES, D FLIP-FLOP, PDSO8. s: Flip-Flop Type: D ; Package Type: 0.50 MM PITCH, PLASTIC, SSOP-8, SSOP ; Number of Pins: 8.

 
0-C     D-L     M-R     S-Z