· 8-bit positive edge-triggered register· 3-State inverting output buffers· Common 3-State Output register· Independent register and 3-State buffer operation

The an 8-bit edge-triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by the Clock (CP) and Output Enable (OE) control gates. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop's Q output. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The

active Low Output Enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in high impedance "off" state, which means they will neither drive nor load the bus. TYPE 74F534 TYPICAL fMAX 165MHz TYPICAL SUPPLY CURRENT (TOTAL) 51mA

PINS OE CP Data inputs Output Enable input (active Low) Clock Pulse input (active rising edge) DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW 20µA/0.6mA 3.0mA/24mA

- Q7 Data outputs NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.

INPUTS OE NC= CP Dn INTERNAL REGISTER NC Dn OUTPUTS NC Z OPERATING MODES Load and read register Hold Disable outputs

High voltage level High voltage level one setup time prior to the Low-to-High clock transition Low voltage level Low voltage level one setup time prior to the Low-to-High clock transition No change Don't care High impedance "off" state Low-to-High clock transition Not a Low-to-High clock transition