|Category||Logic => Transceivers|
|Description||74F543; 74F544; Octal Registered Transceiver, Non-inverting (3-State); Octal Registered Transceiver,inverting (3-State);; Package: SOT137 (SO24), SOT222-1 (DIP24), SOT340-1 (SSOP24)|
|Company||Philips Semiconductors (Acquired by NXP)|
|Datasheet||Download 74F543 datasheet
|Cross ref.||Similar parts: 54F543/BLA, 74F543DB, SN54F543J, SN74F543DBLE, SN74F543DW, SN74F543DW3, SN74F543DWR, SN74F543N3, SN74F543NT|
74F543 Octal registered transceiver, non-inverting (3-State) 74F544 Octal registered transceiver, inverting (3-State)FEATURES
Octal registered transceiver, non-inverting (3-State) Octal registered transceiver, inverting 93-State)
The 74F543 and 74F544 contain two sets of eight D-type latches, with separate input and controls for each set. For data flow from to B, for example, the A-to-B Enable (EAB) input must be Low in order to enter data from A7 or take data from B7, as indicated in the Function Table. With EAB Low, a Low signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B latches transparent; a subsequent Low-to-High transition for the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With EAB and OEAB both Low, the 3-State B output buffers are active and display the data present at the outputs of the A latches. Control of data flow from A is similar, but using the EBA, LEBA, and OEBA inputs. TYPICAL PROPAGATION DELAY 6.0ns 6.5ns TYPICAL SUPPLY CURRENT (TOTAL) 80mA 95mA
Combines74F245 and 74F373 type functions in one chip 8-bit octal transceiver with D-type latch 74F543 Non-inverting Back-to-back registers for storage Separate controls for data flow in each direction A outputs sink 20mA and source 3mA B outputs sink 64mA and source 15mA 3-State outputs for bus-oriented applications 74F543 available in SSOP Type II packageDESCRIPTION
The 74F543 and 74F544 Octal Registered Transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable (LEAB, LEBA) and Output Enable (OEAB, OEBA) inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. While the 74F543 has non-inverting data path, the 74F544 inverts data in both directions. The A outputs are guaranteed to sink 24mA, while the B outputs are rated for 64mA. 74F544 Inverting24-pin plastic skinny DIP (300mil) 24-pin plastic SOL 24-pin plastic SSOP Type II
PINS - B7 OEAB 74F543 74F544 OEBA EAB EBA LEAB LEBA - B7 DESCRIPTION Port A, 3-State inputs Port B, 3-State inputs A-to-B Output Enable input (Active Low) B-to-A Output Enable input (Active Low) A-to-B Enable input (Active Low) B-to-A Enable input (Active Low) A-to-B Latch Enable input (Active Low) B-to-A Latch Enable input (Active Low) Port A, 3-State outputs Port B, 3-State outputs Port A, 3-State outputs Port B, 3-State outputs 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW 3.0mA/24mA 15mA/64mA
NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High State and 0.6mA in the Low state. 1994 DecB7 14 LEAB 13 OEAB VCC = Pin 24 GND = Pin B6 B7 EAB EBA LEAB LEBA OEAB OEBA 13 2
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