|Category||Logic => Transceivers => Registered transceivers|
|Description||74F552; Octal Registered Transceiver With Parity And Flags (3-State);; Package: SOT117-1 (DIP28), SOT136-1 (SO28)|
|Company||Philips Semiconductors (Acquired by NXP)|
|Datasheet||Download 74F552 datasheet
74F552 Octal registered transceiver with parity and flags (3-State)
Octal registered transceiver with parity and flags (3-State)
8-bit bidirectional I/O port with handshake Register status flag flip-flops Separate clock enable and output enable Parity generation and parity check B outputs and parity output sink 64mADESCRIPTION
The 74F522 Octal Registered Transceiver contains two 8-bit registers for temporary storage of data flowing in either direction. Each register has its own clock (CPR, CPS) and Clock Enable (CER, CES) inputs, as well as a flag flip-flop that is set automatically as the register is loaded. The flag output will be reset when the Output Enable returns to High after reading the output port. Each register has a separate Output Enable (OEAS, OEBR) for its 3-State buffer. The separate Clocks, Flags and Enables provide considerable flexibility as I/O ports for demand-response data transfer. When data is transferred from the A port to the B port, a parity bit is generated. On the other hand, when data is transferred from the B port to the A port, the parity of input data B0B7 is checked. TYPICAL SUPPLY CURRENT (TOTAL) 120mA
DESCRIPTION 28-Pin Plastic DIP (600mil) 28-Pin Plastic SOL COMMERCIAL RANGE VCC 5V ±10%, Tamb N74F552N N74F552D
PINS A0A7 B0B7 CPR CPS CER CES OEBR OEAS A Data inputs B Data inputs R registers clock input (active rising edge) S registers clock input (active rising edge) R registers clock Enable input (active Low) S registers clock Enable input (active Low) A-to-B Output Enable input (active Low) and clear FS output (active Low) B-to-A Output Enable input (active Low) and clear FR output (active Low) Parity bit transceiver input PARITY Parity bit transceiver output ERROR FR FS Parity check output (active Low) A Data outputs B Data outputs A-to-B Status Flag output (active High) B-to-A Status Flag output (active High) DESCRIPTION 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW 15mA/64mA 1.0mA/20mANOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
Data applied to the A inputs are entered and stored on the rising edge of the CPR clock pulse, provided that the CER is Low; simultaneously, the status flip-flop is set and the A-to-B flag (FR) output goes High. As the CER returns to High, the data will be held in R register. This data entered from the A inputs will appear at the B port I/O pins after the OEBR has gone Low. When OEBR is Low, a parity bit appears at the PARITY pin, which will be set High when there is an even number 1s or all 0s at the Q outputs of the R register. After the data is assimilated, the receiving system clears the flag FR, by changing the signal at the OEBR pin from Low to High. Data flow from B-to-A proceeds in the same manner described for A-to-B flow. A Low at the CES pin and a Low-to-High transition at the CPS pin enters the B input data and the parity input data into the S register and the parity register respectively and set the flag output FS to High. A Low signal at the OEAS pin enables the A port I/O pins and a Low-to-High transition of the OEAS signal clears the FS flag. When OEAS is Low, the parity check output ERROR will be High if there is an odd number 1s at the Q outputs of the S register and the parity register.
INPUTS or Bn NC= CPX X CEX H L OUTPUTS INTERNAL H NC OPERATING MODE Hold data Load data Keep old data
X L High voltage level Low voltage level No change Don't care or S for CPX and CEX Low-to-High transition Not Low-to-High transitionINPUT OEXX H OUTPUTS INTERNAL L H OPERATING MODE Disable outputs Enable outpus
High voltage level Low voltage level Don't care or BR High impedance "off" state
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