|
|
Part: 74F564
Category:
Logic
-> Flip-Flops
Description: 74F564; Octal D Flip-flop (3-State);; Package: SOT146-1 (DIP20), SOT163-1 (SO20)
Company: Philips Semiconductors
Datasheet: Download 74F564 datasheet File size : 222 kB
Request For quote: Find where to buy 74F564
Datasheet text preview:
INTEGRATED CIRCUITS
74F564 Octal D flip-flop (3-State)
Product specification IC15 Data Handbook 1996 Jan 05
Philips Semiconductors
Philips Semiconductors
Product specification
Octal D flip-flop (3-State)
74F564
FEATURES
· 74F564 is broadside pinout version of 74F534 · Inputs and Outputs on opposite side of package allow easy
interface to Microprocessors
PIN CONFIGURATION
OE 1 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 V CC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CP
· Useful as an Input or Ouput port for Microprocessors · 3-State Ouputs for Bus interfacing · Common Output Enable · 74F574 is a non-inverting version of 74F564
DESCRIPTION
The 74F564 has a broadside pinout configuration to facilitate PC board layout and allows easy interface with microprocessors. It is an 8-bit, edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by the clock (CP) and Output Enable (OE) control gates. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop's Q output. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active Low Output Enable (OE) controls all eight 3-State buffers independently of the register operation. When OE is Low, data in the register appears at the outputs. When OE is High, the outputs are in high impedance "off" state, which means they will neither drive nor load the bus.
GND 10
SF01052
TYPE 74F564
TYPICAL fMAX 180MHz
TYPICAL SUPPLY CURRENT (TOTAL) 50mA
ORDERING INFORMATION
DESCRIPTION 20-Pin Plastic DIP 20-Pin Plastic SOL COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F564N N74F564D PKG. DWG # SOT146-1 SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS D0 - D7 OE CP Data inputs Output Enable input (active Low) Clock Pulse input (active rising edge) DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 150/40 LOAD VALUE HIGH/LOW 20µA/0.6mA 20µA/0.6mA 20µA/0.6mA 3.0mA/24mA
Q0 - Q7 3-State outputs NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
2 3 4 5 6 7 8 9
LOGIC SYMBOL (IEEE/IEC)
1 11 C2 D1 D2 D3 D4 D5 D6 D7 EN1
D0 11 CP
2 3 4
2D
1
19 18 17 16 15 14 13 12
1
OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
5 6 7 19 18 17 16 15 14 13 12 8 9
VCC=Pin 20 GND=Pin 10
SF01053
SF01054
1996 Jan 05
2
853-0166 16189
Philips Semiconductors
Product specification
Octal D flip-flop (3-State)
74F564
LOGIC DIAGRAM
D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
CP
11
OE
1 19 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7
VCC=Pin 20 GND=Pin 10
Q0
SF01055
FUNCTION TABLE
INPUTS OE L L L H H H= h= L= l= NC= X= Z= = = CP Dn l h X X Dn INTERNAL REGISTER L H NC NC Dn OUTPUTS Q0 Q7 H L NC Z Z OPERATING MODES MODES Load and read register Hold Disable outputs
High voltage level High voltage level one setup time prior to the Low-to-High clock transition Low voltage level Low voltage level one setup time prior to the Low-to-High clock transition No change Don't care High impedance "off" state Low-to-High clock transition Not a Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature PARAMETER RATING 0.5 to +7.0 0.5 to +7.0 30 to +5.0 0.5 to +VCC 48 0 to +70 65 to +150 UNIT V V mA V mA °C °C
1996 Jan 05
3
Philips Semiconductors
Product specification
Octal D flip-flop (3-State)
74F564
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARAMETER LIMITS MIN 4.5 2.0 0.8 18 3 24 70 NOM 5.0 MAX 5.5 UNIT V V V mA mA mA °C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) LIMITS SYMBOL PARAMETER
TAG TEST CONDITIONSNO TAG
MIN 2.4 2.7
TYP
NO TAG
MAX
UNIT V
VOH
High-level output voltage output voltage
VCC = MIN, VIL = MAX, VIH = MIN, IOH = MAX VCC = MIN, VIL = MAX, VIH = MIN, IOL = MAX VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX, VO = 2.7V VCC = MAX, VO = 0.5V VCC = MAX VCC = MAX
±10%VCC ±5%VCC ±10%VCC ±5%VCC
3.4 0.35 0.35 0.73 0.50 0.50 1.2 100 20 0.6 50 50
V V V V µA µA mA µA µA mA mA mA
VOL VIK II IIH IIL IOZH IOZL IOS ICC
Low-level output voltage output voltage Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Off-state output current, High-level voltage applied Off-state output current, Low-level voltage applied Short-circuit output currentNO TAG ICCH Supply current (total) ICCL
60 45 50
150 65 75
ICCZ 55 80 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
1996 Jan 05
4
Philips Semiconductors
Product specification
Octal D flip-flop (3-State)
74F564
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb= +25°C VCC = +5V CL = 50pF, RL = 500 MIN fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum Clock frequency Propagation delay CP to Qn Output Enable time to High or Low level Output Disable time from High or Low level Waveform NO TAG Waveform NO TAG Waveform 4 Waveform 5 Waveform 4 Waveform 5 160 3.5 3.5 2.5 4.0 1.0 1.0 TYP 180 5.0 5.0 4.5 5.5 3.0 2.5 8.0 8.0 7.5 8.0 6.0 5.5 MAX Tamb = 0°C to +70°C VCC = +5V ± 10% CL = 50pF, RL = 500 MIN 150 3.0 3.0 2.0 3.5 1.0 1.0 8.5 8.5 8.0 8.5 7.0 6.0 MAX MHz ns ns ns UNIT
AC SETUP REQUIREMENTS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb= +25°C VCC = +5V CL = 50pF, RL = 500 MIN ts(H) ts(L) th(H) th(L) tw(H) tw(L) Setup time, Dn to CP Hold time, Dn to CP CP pulse width, High or Low Waveform 3 Waveform 3 Waveform NO TAG 2.0 2.0 1.0 1.0 3.5 3.5 TYP MAX Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500 MIN 2.0 2.5 1.5 1.5 3.5 3.5 MAX ns ns ns UNIT
AC WAVEFORMS
For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fMAX Dn CP VM tW(H) tPHL Qn VM VM tW(L) tPLH VM Qn VM VM VM VM tPHL VM tPLH
SF01051
SF00990
Waveform 1. Propagation Delay, Clock and Enable Inputs to Output, Enable, Clock Pulse Widths, and Maximum Clock Frequency
Waveform 2. Propagation Delay for Data to Outputs
1996 Jan 05
5
Others parts begin by 74
74-1 74-2 74-3 74-4 74-5 74-6 74-7 74-8 74-9 74-10 74-11 74-12 74-13 74-14 74-15 74-16 74-17 74-18 74-19 74-20 74-21 74-22 74-23 74-24 74-25 74-26 74-27 74-28 74-29 74-30 74-31 74-32 74-33 74-34 74-35 74-36 74-37 74-38 74-39 74-40 74-41 74-42 74-43 74-44 74-45 74-46 74-47 74-48 74-49 74-50 74-51 74-52 74-53 74-54 74-55 74-56 74-57 74-58 74-59 74-60 74-61 74-62
|
|
|
