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Part: 74F569
Category:
Logic
-> Counters
-> Bipolar->F Family
Description: 74F569; 4-bit Bidirectional Binary Synchronous Counter (3-State)
Company: Philips Semiconductors
Datasheet: Download 74F569 datasheet File size : 222 kB
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INTEGRATED CIRCUITS
74F569 4-bit bidirectional binary synchronous counter (3-State)
Product specification IC15 Data Handbook 1996 Jan 05
Philips Semiconductors
Philips Semiconductors
Product specification
4-bit bidirectional binary synchronous counter (3-State)
74F569
FEATURES
· 4-bit bidirectional counting binary counter · Synchronous counting and loading · Look ahead carry capability for easy cascading · Preset capability for programmable operation · Master Reset (MR) overrides all other inputs · Synchronous Reset (SR) overrides counting and parallel loading · Clock Carry (CC) output to be used as a clock for flip-flops,
register and counters
PIN CONFIGURATION
U/D CP D0 D1 D2 D3 CEP MR SR 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 VCC TC CC OE Q0 Q1 Q2 Q3 CET PE
· 3-State outputs for bus organized systems
DESCRIPTION
The 74F569 is a fully synchronous Up/Down binary counter. It features preset capabilities for programmable operation, carry look ahead for programmable operation, carry look ahead for easy cascading, and U/D input to control the direction of counting. For maximum flexibility there are both Synchronous and Master Reset inputs as well as both Clocked Carry (CC) and Terminal Count (TC) outputs. All state changes except Master Reset are initiated by rising edge of the clock. A High signal on the Output Enable (OE) input forces the output buffers into the high impedance state but does not prevent counting, resetting or parallel loading.
GND 10
SF01072
TYPE 74F569
TYPICAL fMAX 115MHz
TYPICAL SUPPLY CURRENT (TOTAL) 40mA
ORDERING INFORMATION
ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F569N N74F569D PKG. DWG. # SOT146-1 SOT163-1
20-pin plastic DIP 20-pin plastic SO
LOGIC SYMBOL
3 4 5 6
LOGIC SYMBOL (IEEE/IEC)
CTR DIV 10 17 EN10 M1[UP] M2[DOWN] 2 CC TC 18 19 12 7 9 Q0 Q1 Q2 Q3 11 C5/1,4,7,8+/2,4,7,8 Z6 G7 G8 5CT=0 M3[LOAD] M4[COUNT] 6,7,8,9 1,7(CT=15)G9 2,7(CT=0)G9 18 19
11 1 2 7 12 8 9 17
PE U/D CP CEP CET MR SR OE
D0
D1
D2
D3
1
VCC = Pin 20 GND = Pin 10
8 16 15 14 13
CT=0 16 15 14 13
SF01056
3 4 5 6 3,5D 10
SF01057
1996 Jan 05
2
8530376 16193
Philips Semiconductors
Product specification
4-bit bidirectional binary synchronous counter (3-State)
74F569
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS D0 - D3 CEP CET CP PE U/D OE MR SR TC CC Parallel data inputs Count Enable parallel input (active Low) Count Enable Trickle input (active Low) Clock input (active rising edge) Parallel Enable input (active Low) Up/Down count control input Output Enable input Master Reset input (active Low) Synchronous Reset (active Low) Terminal count output (active Low) Clocked carry output (active Low) DESCRIPTION 74F(U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/2.0 1.0/1.0 1.0/2.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33 50/33 LOAD VALUE HIGH/LOW 20µA/0.6mA 20µA/0.6mA 20µA/1.2mA 20µA/0.6mA 20µA/1.2mA 20µA/0.6mA 20µA/0.6mA 20µA/0.6mA 20µA/0.6mA 1.0mA/20mA 1.0mA/20mA 3.0mA/24mA
Q0 - Q3 Data outputs 150/40 NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.
FUNCTIONAL DESCRIPTION
The 74F569 counts in the modulo-16 binary sequence. From state 0 (LLLL) it will increment to 15 in the up mode; in the down mode it will decrement from 15 to 0. The clock inputs of all flip-flops are driven parallel through a clock buffer. All state changes (except due to Master Reset) occur synchronously with the Low-to-High transition of the Clock Pulse (CP) input. The circuit has five fundamental modes of operation, in order of precedence: asynchronous reset, synchronous reset, parallel load, count and hold. Six control inputsMaster Reset (MR), Synchronous Reset (SR), Count Enable Trickle (CET), Parallel Enable (PE), Count Enable Parallel (CEP), and the Up/Down (U/D) input determine the mode of operation, as shown in the Function Table. A Low signal on MR overrides all other inputs and asynchronously forces the flip-flop Q outputs Low. A Low signal on SR overrides counting and parallel loading and allows the Q output to go Low on the next rising edge of CP. A Low signal on PE overrides counting and allows information on the parallel data (Dn) inputs to be loaded into the flip-flops on the next rising edge of CP. With MR, SR, and PE High, CEP and CET permit counting when both are Low. Conversely, a High signal on either CEP and CET inhibits counting. The 74F569 uses edge-triggered flip-flops and changing the SR, PE, CEP, CET or U/D inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. Two types of outputs are provided as overflow/underflow indicators. The Terminal Count (TC) output is normally High and goes Low provided CET is Low, when the counter reaches zero in the down mode, or reaches maximum 15 in the up mode TC will then remain Low until a state change occurs by counting or presetting, or until U/D or CET is changed. To implement synchronous multistage counters, the connections between the TC output and the CEP and CET inputs can provide either slow or fast carry propagation. Figure 1 shows the connections for a simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry look ahead connections in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from Max to Min in the up mode, or Min to Max in the down mode, to start its final cycle. Since this takes 16 clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that limits the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, register or counters. For such applications, the Clocked Carry (CC) output is provided. The CC output is normally High. When CEP, CET, and TC are Low, the CC output will go Low, when the clock next goes Low and will stay Low until the clock goes High again; as shown in the CC Function Table. When the Output Enable (OE) is Low, the parallel data outputs Q0Q3 are active and follow the flip-flop Q outputs. A High signal on OE forces Q0Q3 to the High impedance state but does not prevent counting, loading or resetting. LOGIC EQUATIONS: Count Enable=CEP×CET×PE Up: TC=Q0×Q1×Q2×Q3×(Up)×CET Down: TC=Q0×Q1×Q2×Q3×(Down)×CET
1996 Jan 05
3
Philips Semiconductors
Product specification
4-bit bidirectional binary synchronous counter (3-State)
74F569
COUNT
CET
TC
CET
TC
CET
TC
CET
TC
CET
TC
CP
CP
TO ALL STAGES
SF01059
Figure 1. Multistage Counter with Ripple Carry
COUNT
CET
TC
CEP
CEP
CEP
CEP
CP CP TO ALL STAGES
LOW
CET
TC
CET
TC
CET
TC
CET
SF01061
Figure 2. Multistage Counter with Look-Ahead Carry
STATE DIAGRAM
0 1 2 3 4
CC FUNCTION TABLE
INPUTS SR L X PE X L X X X H CEP X X H X X L CET X X X H X L TC* X X X X H L CP X X X X X OUTPUT CC H H H H H
15
5
14
6
X X
13
7
X H * H L X = = = =
12
11
10
9
8
COUNT DOWN COUNT UP
SF01058
TC is generated internally High voltage level Low voltage level Don't care = Low Pulse
FUNCTION TABLE
INPUTS MR L h h h h h h H h L l X = = = = = = SR X l h h h H H PE X X l h h H H CEP X X X l l H X CET X X X l l X H U/D X X X h l X X CP X X Hold (do nothing) (do nothing) X High voltage level High voltage level one setup time prior to the Low-to-High clock transition Low voltage level Low voltage level one setup time prior to the Low-to-High clock transition Don't care Low-to-High clock transition OPERATING MODE MODE Asynchronous reset Synchronous reset Parallel load Count Up (increment) Count Down (decrement)
1996 Jan 05
4
Philips Semiconductors
Product specification
4-bit bidirectional binary synchronous counter (3-State)
74F569
LOGIC DIAGRAM
OE 17 MR 8
D0
3
D
Q 16 Q0
CP Q RD
D1 4
D
Q
CP Q RD
15
Q1
D2
5
D
Q 14 RD Q2
CP Q
D3 SR 9
6
D
Q 13 Q3 RD
CP Q PE 11
7 CEP 12 CET CP U/D 2 1 19 TC
VCC = Pin 20 GND = Pin 10
18 CC
SF01062
1996 Jan 05
5
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