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Part: 74F573
Category:
Logic
-> Latches
Description: 74F573; 74F574; Octal Transparent Latch (3-State); Octal Transparent Latch (3-State);; Package: SOT146-1 (DIP20), SOT163 (SO20), SOT339-1 (SSOP20)
Company: Philips Semiconductors
Datasheet: Download 74F573 datasheet File size : 222 kB
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Datasheet text preview:
INTEGRATED CIRCUITS
74F573 Octal transparent latch (3-State) 74F574 Octal transparent latch (3-State)
Product specification IC15 Data Handbook 1989 Oct 16
Philips Semiconductors
Philips Semiconductors
Product specification
Latch/flip-flop
74F573 Octal Transparent Latch (3-State) 74F574 Octal D Flip-Flop (3-State)
FEATURES
74F573/74F574
· 74F573 is broadside pinout version of 74F373 · 74F574 is broadside pinout version of 74F374 · Inputs and Outputs on opposite side of package allow easy
interface to Microprocessors
The 74F574 is functionally identical to the 74F374 but has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocesors. It is an 8-bit, edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by the clock (CP) and Output Enable (OE) control gates. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop's Q output. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active Low Output Enable (OE) controls all eight 3-State buffers independently of the latch operation. When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in high impedance "off" state, which means they will neither drive nor load the bus. TYPICAL SUPPLY CURRENT (TOTAL) 35mA TYPICAL SUPPLY CURRENT (TOTAL) 50mA
· Useful as an Input or Output port for Microprocessors · 3-State Outputs for Bus interfacing · Common Output Enable · 74F563 and 74F564 are inverting version of 74F573 and 74F574
respectively
· 3-State Outputs glitch free during power-up and power-down · These are High-Speed replacements for N8TS805 and N8TS806
DESCRIPTION
The 74F573 is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled independently by Enable (E) and Output Enable (OE) control gates. The 74F573 is functionally identical to the 74F373 but has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. The data on the D inputs is transferred to the latch outputs when the Enable (E) input is High. The latch remains transparent to the data input while E is High and stores the data that is present one setup time before the High-to-Low enable transition. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active Low Output Enable (OE) controls all eight 3-State buffers independent to the latch operation. When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in high impedance "off" state, which means they will neither drive nor load the bus.
TYPE 74F573
TYPICAL PROPAGATION DELAY 5.0ns
TYPE 74F574
TYPICAL fMAX 180MHz
ORDERING INFORMATION
DESCRIPTION 20-Pin Plastic DIP 20-Pin Plastic SOL 20-Pin Plastic SSOP COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F573N, N74F574N N74F573D, N74F574D N74F573DB PKG DWG # SOT146-1 SOT163-1 SOT339-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS D0 - D7 E (74F573) OE CP (74F574) Data inputs Latch Enable input (active falling edge) Output Enable input (active Low) Clock Pulse input (active rising edge) DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 150/40 LOAD VALUE HIGH/LOW 20µA/0.6mA 20µA/0.6mA 20µA/0.6mA 20µA/0.6mA 3.0mA/24mA
Q0 - Q7 3-State outputs NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
1989 Oct 16
2
853-0083 97897
Philips Semiconductors
Product specification
Latch/flip-flop
74F573/74F574
PIN CONFIGURATION 74F573
OE 1 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 E
PIN CONFIGURATION 74F574
OE 1 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CP
GND 10
GND 10
SF01073
SF01074
LOGIC SYMBOL 74F573
2 3 4 5 6 7 8 9
LOGIC SYMBOL 74F574
3 4 5 6 7 8 9
2
D0 11 E
D1
D2
D3
D4
D5
D6
D7 11 CP
D0
D1
D2
D3
D4
D5
D6
D7
1
OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
1
OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
19 VCC=Pin 20 GND=Pin 10
18
17
16
15
14
13
12 VCC=Pin 20 GND=Pin 10
19
18
17
16
15
14
13
12
SF01075
SF01076
LOGIC SYMBOL (IEEE/IEC) 74F573
1 11 EN1 EN2 19 18 17 16 15 14 13 12
LOGIC SYMBOL (IEEE/IEC) 74F574
1 11 EN1 C2 19 18 17 16 15 14 13 12
2 3 4 5 6 7 8 9
2D
1
2 3 4 5 6 7 8 9
2D
1
SF01077
SF01078
1989 Oct 16
3
Philips Semiconductors
Product specification
Latch/flip-flop
74F573/74F574
LOGIC DIAGRAM 74F573
D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9
D E Q
D E Q
D E Q
D E Q
D E Q
D E Q
D E Q
D E Q
E
11
OE
1 19 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7
VCC=Pin 20 GND=Pin 10
Q0
SF01079
FUNCTION TABLE 74F573
INPUTS OE L L L L L H H H= h= L= l= NC= X= Z= = E H H L L H Dn L H l h X X Dn INTERNAL REGISTER L H L H NC NC Dn OUTPUTS Q0 Q7 L H L H NC Z Z OPERATING MODES MODES Load and read register Latch and read register Hold Disable outputs
High voltage level High voltage level one setup time prior to the High-to-Low E transition Low voltage level Low voltage level one setup time prior to the High-to-Low E transition No change Don't care High impedance "off" state High-to-Low E transition
LOGIC DIAGRAM 74F574
D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
D CP Q
CP
11
OE
1 19 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7
VCC=Pin 20 GND=Pin 10
Q0
SF01080
1989 Oct 16
4
Philips Semiconductors
Product specification
Latch/flip-flop
74F573/74F574
FUNCTION TABLE 74F574
INPUTS OE L L L H= h= L= l= NC= X= Z= = = CP Dn l h X INTERNAL REGISTER L H NC OUTPUTS Q0 Q7 L H NC Z OPERATING MODES MODES Load and read register Hold Disable outputs
H Dn Dn High voltage level High voltage level one setup time prior to the Low-to-High clock transition Low voltage level Low voltage level one setup time prior to the Low-to-High clock transition No change Don't care High impedance "off" state Low-to-High clock transition Not a Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature PARAMETER RATING 0.5 to +7.0 0.5 to +7.0 30 to +5.0 0.5 to +VCC 48 0 to +70 65 to +150 UNIT V V mA V mA °C °C
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARAMETER LIMITS MIN 4.5 2.0 0.8 18 3 24 70 NOM 5.0 MAX 5.5 UNIT V V V mA mA mA °C
1989 Oct 16
5
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