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Part: 74F597
Category:
Logic
-> Registers
-> Shift Registers
Description: 74F597; 8-bit Shift Register With Input Storage Registers;; Package: SOT109 (SO16), SOT38-4 (DIP16)
Company: Philips Semiconductors
Datasheet: Download 74F597 datasheet File size : 202 kB
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INTEGRATED CIRCUITS
74F597 8-bit shift register with input storage registers
Product specification IC15 Data Handbook 1991 Sep 13
Philips Semiconductors
Philips Semiconductors
Product specification
8-bit shift register with input storage registers
74F597
FEATURES
· High impedance PNP base inputs for reduced loading
(20µA in High and Low states)
PIN CONFIGURATION
D1 D2 D3 D4 D5 D6 D7 GND 1 2 3 4 5 6 7 8 16 VCC 15 D0 14 DS 13 SHLD 12 STCP 11 SHCP 10 SHRST 9 QS
· 8-bit parallel storage register · 3-State output buffers · Shift register has asynchronous direct overriding reset · Shift load SHLD is functional when SHCP is Low and locked out
when SHCP is High
· Guaranteed shift frequency DC to 105MHz
DESCRIPTION
The 74F597 consists of an 8-bit storage register feeding a parallel-in/serial-in, serial-out 8-bit shift register. The storage register and shift register have separate positive edge triggered clocks. The shift register has asynchronous reset and when SHCP is Low, it has asynchronous load. The shift register load function has been modified to load when both SHLD and SHCP are Low. When SHCP is High the shift register load operation is not performed. Data will be properly shifted on the rising edge of SHCP when SHLD is High.
SF00366
TYPE 74F597
TYPICAL fMAX 135MHz
TYPICAL SUPPLY CURRENT (TOTAL) 42mA
ORDERING INFORMATION
DESCRIPTION 16-pin plastic DIP 16-pin plastic SO COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F597N N74F597D PKG DWG # SOT38-4 SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS Ds D0D7 SHCP STCP SHLD SHRST Qs Serial data input Parallel data inputs Shift register clock pulse input Storage register clock pulse input Shift register load input (active Low) Shift register reset input (active Low) Serial data output DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/0.033 1.0/0.033 1.0/0.033 1.0/0.033 1.0/0.033 1.0/0.033 50/33 LOAD VALUE HIGH/LOW 20µA/20µA 20µA/20µA 20µA/20µA 20µA/20µA 20µA/20µA 20µA/20µA 1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
1991 Sep 13
2
8531556 03964
Philips Semiconductors
Product specification
8-bit shift register with input storage registers
74F597
LOGIC SYMBOL
14 15 1 2 3 4 5 6 7
IEC/IEEE SYMBOL (IEEE/IEC)
SRG8 10 11 R C3/ ! C2 C1 3D 1D 2D
Ds 10 11 12 13 SHRST SHCP STCP SHLD
D0
D1
D2
D3 D4 D5
D6
D7
13 12 14 15
Qs
1 2
14
3 4
VCC = Pin 16 GND = Pin 8
SF01107
5 6 7 9
SF01108
FUNCTION TABLE
INPUTS OPERATING MODES MODES STCP X X X H L X = = = = = SHCP X L L L X H SHLD X L L L H H X SHRST X H H L L H H Data loaded to storage registers Data loaded from inputs to shift register Data transferred from storage registers to shift registers Invalid logic, state of shift register indeterminate when signals removed Shift register cleared Shift register clocked, Qn=Qn1, Q0=Ds Hold
High voltage level Low voltage level Don't care Low-to-High clock transition Not a Low-to-High clock transition
1991 Sep 13
3
Philips Semiconductors
Product specification
8-bit shift register with input storage registers
74F597
LOGIC DIAGRAM
10 SHRST SHCP SHLD STCP Ds D0 11 13 12 14 15 1D S C1 R C2 2D
D1
1
1D S C1 R
C2 2D
D2
2
1D S C1 R
C2 2D
D3
3
1D S C1 R
C2 2D
D4
4
1D S C1 R
C2 2D
D5
5
1D S C1 R
C2 2D
D6
6 1D S C1 R
C2 2D
D7
7 1D S C1 R
C2 2D
9 Qs
VCC = Pin 16 GND = Pin 8
SF01109
1991 Sep 13
4
Philips Semiconductors
Product specification
8-bit shift register with input storage registers
74F597
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature range PARAMETER RATING 0.5 to +7.0 0.5 to +7.0 30 to +5 0.5 to +VCC 40 0 to +70 65 to +150 UNIT V V mA V mA °C °C
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARAMETER MIN 4.5 2.0 0.8 18 1 20 +70 NOM 5.0 MAX 5.5 V V V mA mA mA °C UNIT
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) LIMITS SYMBOL PARAMETER
TAG TEST CONDITIONSNO TAG
MIN 2.5 2.7
TYP
NO TAG
MAX
UNIT
VOH
High-level output voltage output voltage
VCC = MIN, VIL = MAX MAX, VIH = MIN
±10%VCC IOH = 1mA 1mA ±5%VCC ±10%VCC ±5%VCC
V 3.4 0.30 0.30 0.73 0.50 0.50 1.2 100 20 20 V V V V µA µA µA mA mA mA
VOL VIK II IIH IIL IOS ICC
Low-level output voltage output voltage Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Short-circuit output currentNO TAG Supply current (total) current (total) ICCH ICCL
VCC = MIN, VIL = MAX, , , VIH = MIN, IOL = MAX VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX VCC = MAX MAX
60 43 41
150 65 60
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
1991 Sep 13
5
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