74F646A Octal transceiver/register, non-inverting (3-State) 74F648A Octal transceiver/register, inverting (3-State)
74F646A: Octal transceiver/register, non-inverting (3-State) 74F648A: Octal transceiver/register, inverting (3-State)
FEATURES
· Combines 74F245 and two 74F374 type functions in one chip· High impedance base inputs for reduced loading µA in HIGH
DESCRIPTION
The 74F646A and 74F648A transceivers/registers consist of bus transceiver circuits with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the or B bus will be clocked into the registers as the appropriate clock pin goes HIGH. Output enable (OE) and DIR pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the or B register or both. The select pins (SAB, SBA) determine whether data is stored or transferred through the device in real-time. The DIR determines which bus will receive data when the OE is active LOW. In the isolation mode (OE = HIGH), data from bus A may be stored in the B register and/or data from bus B may be stored in the A register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, or B may be driven at a time.
· Independent registers for A and B buses· Multiplexed real-time and stored data· Choice of non-inverting and inverting data paths· Controlled ramp outputs for 74F646A/74F648A· 3-state outputs· 300 mil wide 24-pin slim DIP package
ORDER CODE DESCRIPTION 24-pin plastic slim DIP (300 mil) 24-pin plastic SOL COMMERCIAL RANGE VCC V ±10%, Tamb SOT222-1 SOT137-1 PKG DWG #
PINS A0-A7, B0-B7 CPAB CPBA SAB SBA DIR B7 A and B inputs A-to-B clock input B-to-A clock input A-to-B select input B-to-A select input Data flow directional control enable input Output enable input A, B outputs for N74F646A/N74F648A DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH / LOW 48 mA
NOTE: One (1.0) FAST unit load is defined as: µA in the HIGH state and mA in the LOW state.
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