Details, datasheet, quote on part number: 74F670
Part74F670
CategoryLogic => Registers => Shift Registers
Description74F670; 4 X 4 Register File (3-State);; Package: SOT162-1 (SO16), SOT38-1 (DIP16)
CompanyPhilips Semiconductors (Acquired by NXP)
DatasheetDownload 74F670 datasheet
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Features, Applications

FEATURES

Simultaneous and Independent Read and Write operations Expandable to almost any word size and bit length 3-State outputs

DESCRIPTION

The 16-bit 3-State Register File organized as 4 words of 4 bits each. Separate Read and Write Address and Enable inputs are available, permitting simultaneous writing into one word location and reading from another location. The 4-bit word to be stored is presented to four data inputs. The Write address inputs (WA and WB) determine the location of the stored word. The Write Address inputs should only be changed when the Write Enable input (WE) is High for conventional operation. When the WE is Low, the data is entered into the addressed location. The addressed location remains transparent to the data while the WE is Low. Data supplied at the inputs will be read out in true (non-inverting) form from the 3-State outputs. Data and address inputs are inhibited when the WE is High. Direct acquisition of data stored in any of the four registers is made possible by individual Read Address inputs (RA, RB). The addressed word appears at the four outputs when the Read Enable (RE) is Low. Data outputs are in the high impedance "off" state when the RE is High. This permits outputs to be tied together to increase the word capacity to very large numbers. to 128 devices can be stacked to increase the word size to 512 locations by tying the 3-State outputs together. Since the limiting factor for expansion is the output High current, further stacking is possible by tying pullup reisistors to the outputs to increase the IOH current available. Design of the Read Enable signals for the stacked devices must ensure that there is no overlap in the Low levels which cause more than one output to be active at the same time. Parallel expansion to generate n-bit words is accomplished by driving the Enable and address inputs of each device in parallel.

DESCRIPTION 16-pin plastic DIP 16-pin plastic SOL COMMERCIAL RANGE VCC 5V 10%, Tamb N74F670N N74F670D PKG DWG SOT38-4 SOT162-1

PINS - D3 WA, WB RA, RE Q0Q3 DESCRIPTION Data inputs Write address inputs Read address inputs Write Enable inputs Read Enable inputs Data output 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW 20mA/0.6mA 3.0mA/24mA

NOTE: One (1.0) FAST Unit Load is defined as: 20A in the High state and 0.6mA in the Low state.
WRITE MODE H L READ MODE H RA OPERATING MODE Word Selected Word 0 Word 1 Word 2 Word 3
INPUT RE INTERNAL LATCHES* L H OUTPUT OPERATING MODE L H Read

X NC Data latched H = High voltage level L = Low voltage level NC= No change X = Don't care * = The write address (WA and WB) to the "internal latches" must be stabled while WE is Low for conventional operation.

X Z Disabled High voltage level Low voltage level Don't care High impedance "off" state The selection of "internal latches" by Read Address (RA and RB) are not constrained or RE operation.


 

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