|Category||Logic => Registers => Shift Registers|
|Description||74F676; 16-bit Serial/parallel-in, Serial-out Shift Register (3-State);; Package: SOT137 (SO24), SOT222-1 (DIP24)|
|Company||Philips Semiconductors (Acquired by NXP)|
|Datasheet||Download 74F676 datasheet
16-bit parallel-to-serial conversion 16-bit serial-in, serial-out Chip select control Power supply current 48mA typical Shift frequency 110MHz tyical Available 300mil-wide 24-pin Slim DIP packageDESCRIPTION
The 74F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output. When the mode (M) input is High, information present on the parallel data (D0D15) inputs is entered on the falling edge of the clock pulse (CP) input signal. When M is Low, data is shifted out of the most significant bit position while information present on the serial (SI) input shifts into the least significant bit position. A High signal on the chip select (CS) input prevents both parallel and serial operations. The 16 bit shift register operates in one of three modes, as indicated in the shift register Function Table. Hold: A High signal on the Chip Select (CS) input prevents clocking and data is stored in the 16 registers. Serial load: Data present on the SI pin shifts into the register on the falling edge of CP. Data enters the Q0 position and shifts toward Q15 on successive clocks finally appearing on the SO pin. Parallel load: Data present D0D15 is entered into the register on the falling edge of CP. The SO output represents the Q15 register output. To prevent false clocking, CP must be Low during a Low-to-High transition of CS.
DESCRIPTION 24-Pin Plastic Slim DIP (300mil) 24-Pin Plastic SOL COMMERCIAL RANGE VCC 5V ±10%, Tamb N74F676N N74F676D PKG DWG SOT222-1 SOT137-1
PINS M SO Parallel data inputs Serial data input Chip Select input (active Low) Clock Pulse input (active falling edge) Mode select input Serial data output DESCRIPTION 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW 20µA/0.6mA 1mA/20mANOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
CONTROL INPUTS CP X Hold Shift/Serial load OPERATING MODE
L H Parallel load High voltage level Low voltage level Don't care High-to-Low transition of clock input
|Related products with the same datasheet|
|Some Part number from the same manufacture Philips Semiconductors (Acquired by NXP)|
|74F711-1 74F676; 16-bit Serial/parallel-in, Serial-out Shift Register (3-State);; Package: SOT137 (SO24), SOT222-1 (DIP24)|
|74F7111 74F711A; 74F711-1; 74F712A; 74F712-1; Multiplexers;; Package: SOT146-1 (DIP20), SOT163 (SO20)|
|74F723-1 74F723A; 74F723-1; 74F725A; 74F725-1; Various Quad Data Selector Multiplexers (3-State)|
|74F74 74F74; Dual D-type Flip-flop;; Package: SOT27-1 (DIP14)|
|74F756 74F756; 74F757; 74F760; Octal Inverter Buffer (open-collector); Octal Buffer (open-collector); Octal Buffer (open-collector);; Package: SOT146-1 (DIP20), SOT163 (SO20)|
|74F764-1 DRAM Dual-ported Controller|
|74F776 74F776; Pi-bus Transceiver;; Package: SOT117-1 (DIP28), SOT261-2 (PLCC28)|
|74F777 74F777; Triple Bidirectional Latched Bus Transceiver (3-State + Open Collector);; Package: SOT146-1 (DIP20), SOT380-1 (PLCC20)|
|74F779 74F779; 8-bit Bidirectional Binary Counter (3-State);; Package: SOT38-1 (DIP16)|
|74F786 74F786; 4-bit Asynchronous Bus Arbiter;; Package: SOT109 (SO16), SOT38-4 (DIP16)|
|74F804 74F804; 74F1804; Hex 2-input NAND Drivers;; Package: SOT146-1 (DIP20), SOT163 (SO20)|
|74F805 74F805; 74F1805; Hex 2-input Nor Drivers;; Package: SOT146-1 (DIP20), SOT163 (SO20)|
|74F808 74F808; 74F1808; Hex 2-input And Drivers;; Package: SOT146-1 (DIP20), SOT163 (SO20)|
|74F821 74F821; 74F822; 74F823; 74F824; 74F825; 74F826; Bus Interface Registers;; Package: SOT222-1 (DIP24)|
|74F827 74F827; 74F828; 10-bit Buffer/line Driver, Non-inverting (3-State); 10-bit Buffer/line Driver, Inverting (3-State);; Package: SOT137 (SO24), SOT222-1 (DIP24), SOT340-1 (SSOP24)|
|74F832 74F832; 74F1832; Hex 2-input or Drivers;; Package: SOT146-1 (DIP20), SOT163 (SO20)|
|74F835 8-bit Shift Register With 2:1 Mux-in, Latched B Inputs, And Serial Out|
|74F841 74F841/74F842/74F843/74F845/74F846; Bus Interface Latches;; Package: SOT137 (SO24), SOT222-1 (DIP24)|
|74F85 74F85; 4-bit Magnitude Comparator;; Package: SOT162-1 (SO16), SOT38-1 (DIP16)|
|74F86 74F86; Quad 2-input Exclusive-OR GATE;; Package: SOT108-1 (SO14), SOT27-1 (DIP14)|
|74F862 74F862; 74F863; Bus Transceivers (3-State);; Package: SOT137 (SO24), SOT222-1 (DIP24)|
5962-8406201VEA : Decoders. ti SN54HC138, 3-Line to 8-Line Decoders/demultiplexers. Memory Decoders and Data-Transmission Systems Wide Operating Voltage Range 6 V Outputs Can Drive To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd ns ±4-mA Output Drive 5 V Low Input Current 1 µA Max Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception The 'HC138 devices are designed to be used in high-performance.
74HC1G32 : 74HC1G32; 74HCT1G32; 2-input OR GATE;; Package: SOT353 (UMT5), SOT753.
74LVQ14 : LVQ->HCMOS->Low Voltage. Hex Schmitt Inverter. HIGH SPEED: tPD 6 ns (TYP.) at VCC 3.3 V HYSTERESIS INPUT VOLTAGE: = 650mV (TYP.) at VCC 3.0 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC at TA=25°C LOW NOISE: VOLP = 0.3V (TYP.) at VCC 3.3V 75 TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12mA (MIN) at VCC 3.0 V PCI BUS LEVELS GUARANTEED 24 mA BALANCED.
74VHCT16245A : VHC/VHCT->Low Noise HCMOS. 16-BIT Bus Transceiver (3-STATE). HIGH SPEED: tPD 4.5 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC 4 µA (MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN.), VIL = 0.8V (MAX) POWER DOWN PROTECTION ON INPUTS & OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) to 5.5V IMPROVED LATCH-UP IMMUNITY.
8403701CA : ti CD54HC00, High Speed CMOS Logic Quad 2-Input NAND Gates. Data sheet acquired from Harris Semiconductor SCHS116C High-Speed CMOS Logic Quad 2-Input NAND Gate The CD74HC00, CD54HCT00, and CD74HCT00 logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL.
HD74LV1GT02A : . Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips.
M24512BN : 512 Kbit Serial ic Bus EePROM. Compatible with I2C Extended Addressing Two Wire I2C Serial Interface Supports 400 kHz Protocol Single Supply Voltage: to 5.5V for to 5.5V for to 3.6V for M24512-R Hardware Write Control BYTE and PAGE WRITE (up to 128 Bytes) RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Behaviour 100000.
MC100ELT20DTR2 : 5V TTL to Differential Pecl Translator, Package: Tssop 8, Pins=8. The is a TTL to differential PECL translator. Because PECL (Positive ECL) levels are used, only +5 V and ground are required. The small outline 8-lead package and the single gate of the ELT20 makes it ideal for those applications where space, performance and low power are at a premium. The 100 Series contains temperature compensation. 1.2 ns Typical.
MC74VHCT259AM : 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter, Package: SOEIAJ-16, Pins=16.
SN100KT5578 : Bipolar->ECL 10 Family. Octal Ttl-to-ecl Translator With D-type Edge-triggered Flip-flops And Output Enable.
SN74ABTH16245 : Bus Oriented Circuits. 16-bit Bus Transceivers With 3-state Outputs. Members of the Texas Instruments Widebus TM Family State-of-the-Art EPIC-B TM BiCMOS Design Significantly Reduces Power Dissipation Typical VOLP (Output Ground Bounce) V at VCC = 25°C High-Impedance State During Power Up and Power Down Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes.
SN74AHCT1G126 : Bus Oriented Circuits. Single Bus Buffer Gate With 3-state Output. Operating Range 5.5 V Max tpd 5 V Low Power Consumption, 10-µA Max ICC ±8-mA Output Drive 5 V Inputs Are TTL-Voltage Compatible Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 2000-V Human-Body Model 200-V Machine Model 1000-V Charged-Device Model (C101) The is a single bus buffer gate/line driver with 3-state output.
SN74BCT29834 : Bus Oriented Circuits. 8-bit to 9-bit Parity Bus Transceiver. BiCMOS Process With TTL Inputs and Outputs BiCMOS Design Reduces Standby Current Flow-Through Pinout (All Inputs on Opposite Side From Outputs) Functionally Equivalent to SN74ALS29834 and AMD Am29834 High-Speed Bus Transceiver With Parity Generator/ Checker Parity-Error Flag With Open-Collector Output Available Register For Storage of the Parity-Error.
TC74HC7244 : CMOS/BiCMOS->HC/HCT Family. Octal Bus Buffer (with Schmitt Trigger Inputs).
A2F500M3G-FG256Y : FPGA, 11520 CLBS, 500000 GATES, PBGA256. s: System Gates: 500000 ; Logic Cells / Logic Blocks: 11520 ; Package Type: Other, 1 MM PITCH, FBGA-256 ; Logic Family: CMOS ; Pins: 256 ; Operating Temperature: 0 to 85 C (32 to 185 F) ; Supply Voltage: 1.5V.
935249730112 : 4000/14000/40000 SERIES, ASYN NEGATIVE EDGE TRIGGERED 12-BIT UP BINARY COUNTER, PDSO16. s: Counter Type: BINARY COUNTER ; Counter Category: Asynchronous ; Counter Direction: UP ; Supply Voltage: 5V ; Package Type: PLASTIC, SOT-109, SO-16 ; Logic Family: CMOS, 4000/14000/40000 ; Number of Pins: 16 ; Number of Stages (Bits): 12 bits ; Clock Frequency:.