|Category||Logic => Transceivers|
|Description||74F776; Pi-bus Transceiver;; Package: SOT117-1 (DIP28), SOT261-2 (PLCC28)|
|Company||Philips Semiconductors (Acquired by NXP)|
|Datasheet||Download 74F776 datasheet
Drives heavily loaded backplanes with equivalent load impedances down to 10 ohms High drive (100mA) open collector drivers on B port Reduced voltage swing (1 volt) produces less noise and reduces power consumption High speed operation enhances performance of backplane buses and facilitates incident wave switching Compatible with Pibus and IEEE 896 Futurebus standards Builtin precision bandgap reference provides accurate receiver thresholds and improved noise immunity Controlled output ramp and multiple GND pins minimize ground bounce Glitchfree power up/power down operation Multiple package options Industrial temperature range available to +85°C)
consumption and a series diode on the drivers to reduce capacitive loading. Incident wave switching is employed, therefore BTL propagation delays are short. Although the voltage swing is less for BTL, so is its receiver threshold, therefore noise margins are excellent. BTL offers low power consumption, low ground bounce, EMI and crosstalk, low capacitive loading, superior noise margin and low propagation delays. This results in a high bandwidth, reliable backplane. The 74F776 A port has TTL 3state drivers and TTL receivers with a latch function. A separate highlevel control voltage input (VX) is provided to limit the A side output level to a given voltage level (such as 3.3V). For 5.0V systems, VX is simply tied to VCC. The 74F776 has a designed feature to control the B output transitions during power sequencing. There are two possible sequencing, They are as follows: LE = low and OEBn = low then the B outputs are disabled until the LE circuitry takes control. Then the B outputs will follow the A inputs, making a maximum of one transition during powerup (or down). LE = high or OEBn = high then the B outputs will be disabled during powerup (or down).DESCRIPTION
The is an octal bidirectional latched transceiver and is intended to provide the electrical interface to a high performance wiredOR bus. The B port inverting drivers are lowcapacitance open collector with controlled ramp and are designed to sink 100mA from 2 volts. The B port inverting receivers have 100 mV threshold region and a 4ns glitch filter. The 74F776 B port interfaces to 'Backplane Transceiver Logic' (BTL). BTL features a reduced to 2V) voltage swing for lower power
ORDER CODE COMMERCIAL RANGE DESCRIPTION VCC 5V ±10%, Tamb N74F776N N74F776A INDUSTRIAL RANGE VCC 5V ±10%, Tamb I74F776N I74F776A PKG DWG #
PINS B7 OEA A7 PNP latched inputs Data inputs with threshold circuitry A output enable input (active high) B output enable inputs (active low) Latch enable input (active low) 3state outputs DESCRIPTION 74F (U.L.) HIGH/LOW OC/166.7 LOAD VALUE HIGH/LOW 3mA/24mA OC/100mA
B7 Open collector outputs Notes to input and output loading and fan out table One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state. OC = Open collector.
SYMBOL OEB0 OEB1 OEA LE VX PINS TYPE I/O Input Enables the A outputs when high Latched when high (a special feature is built in for proper enabling times) Clamping voltage keeping VOH from rising above VX (VX = Vcc for normal use) NAME AND FUNCTION PNP latched input/3state output (with VX control option) Data input with special threshold circuitry to reject noise/ open collector output, high current drive Enables the B outputs when both pins are low
|Some Part number from the same manufacture Philips Semiconductors (Acquired by NXP)|
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