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Part: 74F842
Category:
Logic
-> Latches
Description: 74F841/74F842/74F843/74F845/74F846; Bus Interface Latches;; Package: SOT137 (SO24), SOT222-1 (DIP24)
Company: Philips Semiconductors
Datasheet: Download 74F842 datasheet File size : 180 kB
Request For quote: Find where to buy 74F842
Datasheet text preview:
INTEGRATED CIRCUITS
74F841/842/843/845/846 Bus interface latches
Product specification
Replaces datasheet 74F841/842/843/844/845/846 of 1999 Jan 08
1999 Jun 23
IC15 Data Handbook
Philips Semiconductors
Philips Semiconductors
Product specification
Bus interface latches
74F841/74F842/74F843/ 74F845/74F846
74F841/74F842 10-bit bus interface latches, non-inverting/inverting (3-State) 74F843 9-bit bus interface latch, non-inverting (3-State) 74F845/74F846 8-bit bus interface latches, non-inverting/inverting (3-State)
FEATURES
· High speed parallel latches · Extra data width for wide address/data paths or buses carrying
parity
DESCRIPTION
The 74F84174F846 bus interface latch series are designed to provide extra data width for wider address/data paths of buses carrying parity. The 74F84174F846 series are funcitonally an pin compatible to the AMD AM29841AM29846 series. The 74F841 consists of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is High. This allows asynchronous operation, as the output transition follows the data in transition. On the LE High-to-Low transition, the data that meets the setup and hold time is latched. Data appears on the bus when the Output Enable (OE) is Low. When OE is High the output is in the High-impedance state. The 74F842 is the inverted output version of the 74F841. The 74F843 consists of nine D-type latches with 3-State outputs. In addition to the LE and OE pins, the 74F843 has a Master Reset (MR) pin and Preset (PRE) pin. These pins are ideal for parity bus interfacing in high performance systems. When MR is Low, the outputs are Low if OE is Low. When MR is High, data can be entered into the latch. When PRE is Low, the outputs are High, if OE is Low, PRE overrides MR. The 74F845 consists of eight D-type latches with 3-State outputs. In addition to the LE, OE, MR and PRE pins, the 74F845 has two addtitional OE pins making a total of three Output Enables (OE0, OE1, OE2) pins. The multiple Ouptut Enables (OE0, OE1, OE2) allow multi-user control of the interface, e.g., CS, DMA, and RD/WR. The 74F846 is the inverted output version of the 74F845.
· High impedance NPN base input structure minimizes bus loading · IIL is 20µA vs 1000A for AM29841 series · Buffered control inputs to reduce AC effects · Ideal where high speed, light loading, or increased fan-in are
required as with MOS microprocessors
· Positive and negative over-shoots are clamped to ground · 3-State outputs glitch free during power-up and power-down · 48mA sink current · Slim dual in-line 300 mil package · Broadside pinout · Pin-for-pin and function compatible with AMD AM29841-846
series
TYPE 74F841, 74F842 74F843, 74F845 74F846
TYPICAL PROPAGATION DELAY 5.5ns 5.5ns 6.2ns
TYPICAL SUPPLY CURRENT (TOTAL) 60mA 75mA 60mA
ORDERING INFORMATION
PACKAGES 24-pin plastic Slim DIP (300 mil) 24-pin plastic SOL COMMERCIAL RANGE VCC = 5V±10%; Tamb = 0°C to +70°C N74F841N, N74F842N, N74F843N, N74F845N, N74F846N N74F841D, N74F842D, N74F843D, N74F845D, N74F846D PACKAGE DRAWING NUMBER SOT222-1 SOT137-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS Dn LE OE, OEn MR PRE Qn Qn Data inputs Latch Enable input Output Enable input (active Low) Master Reset input (active Low) Preset input (active Low) Data outputs Data outputs DESCRIPTION 74F(U.L.) HIGH/LOW 1.0/0.033 1.0/0.033 1.0/0.033 1.0/0.033 1.0/0.033 1200/80 1200/80 LOAD VALUE HIGH/LOW 20µA/20µA 20µA/20µA 20µA/20µA 20µA/20µA 20µA/20µA 24mA/48mA 24mA/48mA
NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
1999 Jun 23
2
8531208 21851
Philips Semiconductors
Product specification
Bus interface latches
74F841/74F842/74F843/ 74F845/74F846
PIN CONFIGURATION for 74F841
OE 1 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 24 VCC 23 Q0 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8 14 Q9 13 LE
PIN CONFIGURATION for 74F842
OE 1 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 24 VCC 23 Q0 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8 14 Q9 13 LE
D8 10 D9 11 GND 12
D8 10 D9 11 GND 12
SF01279
SF01282
LOGIC SYMBOL for 74F841
2 3 4 5 6 7 8 9 10 11
LOGIC SYMBOL for 74F842
2 3 4 5 6 7 8 9 10 11
D0 13 1 LE OE Q0
D1
D2
D3
D4
D5
D6
D7
D8
D9 13 1 LE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
23 VCC = Pin 24 GND = Pin 12
22
21
20
19
18
17
16
15
14
23 VCC = Pin 24 GND = Pin 12
22
21
20
19
18
17
16
15
14
SF01280
SF01283
LOGIC SYMBOL (IEEE/IEC) for 74F841
1 13 EN C1
LOGIC SYMBOL (IEEE/IEC) for 74F842
1 13 EN C1
2 3 4 5 6 7 8 9 10 11
1D
23 22 21 20 19 18 17 16 15 14
2 3 4 5 6 7 8 9 10 11
1D
23 22 21 20 19 18 17 16 15 14
SF01281
SF01284
1999 Jun 23
3
Philips Semiconductors
Product specification
Bus interface latches
74F841/74F842/74F843/ 74F845/74F846
PIN CONFIGURATION for 74F843
OE 1 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 24 VCC 23 Q0 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8 14 PRE 13 LE
D8 10 MR 11 GND 12
SF01285
LOGIC SYMBOL for 74F843
2 3 4 5 6 7 8 9 10
13 14 11 1
LE PRE MR OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
23 VCC = Pin 24 GND = Pin 12
22
21
20
19
18
17
16
15
SF01286
LOGIC SYMBOL (IEEE/IEC) for 74F843
1 11 14 S2 13 C1 23 22 21 20 19 18 17 16 15 EN R
2 3 4 5 6 7 8 9 10
1D
SF01287
1999 Jun 23
4
Philips Semiconductors
Product specification
Bus interface latches
74F841/74F842/74F843/ 74F845/74F846
PIN CONFIGURATION for 74F845
OE0 OE1 D0 D1 D2 D3 D4 D5 D6 1 2 3 4 5 6 7 8 9 24 VCC 23 OE2 22 Q0 21 Q1 20 Q2 19 Q3 18 Q4 17 Q5 16 Q6 15 Q7 14 PRE 13 LE
PIN CONFIGURATION for 74F846
OE0 OE1 D0 D1 D2 D3 D4 D5 D6 1 2 3 4 5 6 7 8 9 24 VCC 23 OE2 22 Q0 21 Q1 20 Q2 19 Q3 18 Q4 17 Q5 16 Q6 15 Q7 14 PRE 13 LE
D7 10 MR 11 GND 12
D7 10 MR 11 GND 12
SF01291
SF01294
LOGIC SYMBOL for 74F845
3 4 5 6 7 8 9 10
LOGIC SYMBOL for 74F846
3 4 5 6 7 8 9 10
13 14 11 1 2 23
LE PRE MR OE0 OE1 OE2
D0
D1
D2
D3
D4
D5
D6
D7
13 14 11 1 2 23
LE PRE MR OE0 OE1 OE2
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
VCC = Pin 24 GND = Pin 12
22
21
20
19
18
17
16
15
VCC = Pin 24 GND = Pin 12
22
21
20
19
18
17
16
15
SF01292
SF01295
LOGIC SYMBOL (IEEE/IEC) for 74F845
1 2 23 14 11 13 S2 R C1 22 21 20 19 18 17 16 15
LOGIC SYMBOL (IEEE/IEC) for 74F846
1 2 23 14 11 13 S2 R C1 22 21 20 19 18 17 16 15
&
EN
&
EN
3 4 5 6 7 8 9 10
1D
3 4 5 6 7 8 9 10
1D
SF01293A
SF01296A
1999 Jun 23
5
Others parts begin by 74
74-1 74-2 74-3 74-4 74-5 74-6 74-7 74-8 74-9 74-10 74-11 74-12 74-13 74-14 74-15 74-16 74-17 74-18 74-19 74-20 74-21 74-22 74-23 74-24 74-25 74-26 74-27 74-28 74-29 74-30 74-31 74-32 74-33 74-34 74-35 74-36 74-37 74-38 74-39 74-40 74-41 74-42 74-43 74-44 74-45 74-46 74-47 74-48 74-49 74-50 74-51 74-52 74-53 74-54 74-55 74-56 74-57 74-58 74-59 74-60 74-61 74-62
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