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Part: 74HC133D
Category:
Description: 74HC133; 13-input NAND Gate
Company: Philips Semiconductors
Datasheet: Download 74HC133D datasheet File size : 156 kB
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
· The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications · The IC06 74HC/HCT/HCU/HCMOS Logic Package Information · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC133 13-input NAND gate
Product specification File under Integrated Circuits, IC06 September 1993
Philips Semiconductors
Product specification
13-input NAND gate
FEATURES · Output capability: standard · ICC category: SSI GENERAL DESCRIPTION
74HC133
The HC133 is an high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC133 provides the 13-input NAND function. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns SYMBOL tPHL/tPLH CI CPD PARAMETER propagation delay A..M to Y input capacitance power dissipation per gate notes 1 and 2 CONDITIONS CL = 15 pF; VCC = 5 V 9 3.5 19 TYPICAL ns pF pF UNIT
Notes to the quick reference data 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL × VCC2 × fo) = sum of the outputs. 2. For HC the condition is VI = GND to VCC ORDERING INFORMATION PACKAGES TYPE NUMBER PINS 74HC133N 74HC133D 16 16 DIL SO PIN POSITION MATERIAL plastic plastic SOT38 SOT109A CODE
See also "74HC/HCT/HCU/HCMOS Logic Package Information".
September 1993
2
Philips Semiconductors
Product specification
13-input NAND gate
PINNING PIN NO. 1..7, 10.. 15 8 9 16 GND Y VCC SYMBOL A.. G, H..M data input ground (0 V) data output positive supply voltage NAME AND FUNCTION
74HC133
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
September 1993
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Philips Semiconductors
Product specification
13-input NAND gate
74HC133
Fig.4
Functional diagram; Y = ABCDEFGHIJKLM.
Fig.5 Logic diagram.
FUNCTION TABLE INPUTS A L X X X X X X X X X X X X H Notes 1. H = HIGH voltage level L = LOW voltage level X = don't care B X L X X X X X X X X X X X H C X X L X X X X X X X X X X H D X X X L X X X X X X X X X H E X X X X L X X X X X X X X H F X X X X X L X X X X X X X H G X X X X X X L X X X X X X H H X X X X X X X L X X X X X H I X X X X X X X X L X X X X H J X X X X X X X X X L X X X H K X X X X X X X X X X L X X H L X X X X X X X X X X X L X H M X X X X X X X X X X X X L H OUTPUT Y H H H H H H H H H H H H H L
September 1993
4
Philips Semiconductors
Product specification
13-input NAND gate
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: SSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tf = tr = 6 ns; CL = 50 pF Tamb (°C) SYMBOL PARAMETER - - - - - - +25 MIN. TYP. tPHL/tPLH propagation delay A..M to Y output transition time 36 13 10 19 7 6 MAX. 110 22 19 75 15 13 - - - - - - -40 to +85 MIN. MAX. 140 28 23 95 19 16 -40 to +125 MIN. - - - - - - MAX. 165 33 28 110 22 19 ns UNIT
74HC133
TEST CONDITIONS VCC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6
tTHL/tTLH
ns
Fig.6
(1) HC: VM = 50%; VI = GND to VCC.
Fig.6
Waveforms showing the input (A, B, C, D, E, F, G, H, I, J, K, L, M) to output (Y) propagation delays and the output transition times.
PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines".
September 1993
5
Others parts begin by 74
74-1 74-2 74-3 74-4 74-5 74-6 74-7 74-8 74-9 74-10 74-11 74-12 74-13 74-14 74-15 74-16 74-17 74-18 74-19 74-20 74-21 74-22 74-23 74-24 74-25 74-26 74-27 74-28 74-29 74-30 74-31 74-32 74-33 74-34 74-35 74-36 74-37 74-38 74-39 74-40 74-41 74-42 74-43 74-44 74-45 74-46 74-47 74-48 74-49 74-50 74-51 74-52 74-53 74-54 74-55 74-56 74-57 74-58 74-59 74-60 74-61 74-62
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