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Details, datasheet, quote on part number:74HC4015U
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| Part: | 74HC4015U |
| Category: | Logic => Registers => Shift Registers |
| Description: | 74HC/HCT4015; Dual 4-bit Serial-in/parallel-out Shift Register;; Package: SOT109-1 (SO16), SOT338-1 (SSOP16), SOT38-4 (DIP16) |
| Company: | Philips Semiconductors |
| Datasheet: | Download 74HC4015U datasheet File size : 50 kB |
| Request For quote: | Find where to buy 74HC4015U
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Datasheet text preview:
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
· The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications · The IC06 74HC/HCT/HCU/HCMOS Logic Package Information · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4015 Dual 4-bit serial-in/parallel-out shift register
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
Dual 4-bit serial-in/parallel-out shift register
FEATURES · Output capability: standard · ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4015 are high-speed Si-gate CMOS devices and are pin compatible with the "4015" of the "4000B" series. They are specified in compliance with JEDEC standard no. 7A.
74HC/HCT4015
The 74HC/HCT4015 are dual edge-triggered 4-bit static shift registers (serial-to-parallel converters). Each shift register has a serial data input (1D and 2D), a clock input (1CP and 2CP), four fully buffered parallel outputs (1Q0 to 1Q3 and 2Q0 to 2Q3) and an overriding asynchronous master reset (1MR and 2MR). Information present on nD is shifted to the first register position, and all data in the register is shifted one position to the right on the LOW-to-HIGH transition of nCP. A HIGH on nMR clears the register and forces nQ0 to nQ3 to LOW, independent of nCP and nD.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay nCP to nQn maximum clock frequency input capacitance power dissipation capacitance per register notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 16 110 3.5 35 HCT 18 74 3.5 40 ns MHz pF pF UNIT
December 1990
2
Philips Semiconductors
Product specification
Dual 4-bit serial-in/parallel-out shift register
PIN DESCRIPTION PIN NO. 5, 4, 3, 10 6, 14 7, 15 8 9, 1 13, 12, 11, 2 16 SYMBOL 1Q0 to 1Q3 1MR, 2MR 1D, 2D GND 1CP, 2CP 2Q0 to 2Q3 VCC NAME AND FUNCTION flip-flop outputs asynchronous master reset inputs (active HIGH) serial data inputs ground (0 V) clock inputs (LOW-to-HIGH, edge-triggered) flip-flop outputs positive supply voltage
74HC/HCT4015
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Dual 4-bit serial-in/parallel-out shift register
74HC/HCT4015
Fig.5 Fig.4 Functional diagram.
Logic diagram (one 4-bit serial-in/parallel-out shift register).
FUNCTION TABLE INPUTS n 1 2 3 4 nCP X Notes 1. H = HIGH voltage level L = LOW voltage level X = don't care = LOW-to-HIGH clock transition = HIGH-to-LOW clock transition n = number of clock pulse transitions Dn = either HIGH or LOW APPLICATIONS · Serial-to-parallel converter · Buffer stores · General purpose register nD D1 D2 D3 D4 X X nMR nQ0 L L L L L H L L D1 D2 D3 D4 OUTPUTS nQ1 X D1 D2 D3 nQ2 X X D1 D2 L nQ3 X X X D1 L
no change
December 1990
4
Philips Semiconductors
Product specification
Dual 4-bit serial-in/parallel-out shift register
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) 74HC SYMBOL PARAMETER min. tPHL/ tPLH propagation delay nCP to nQn propagation delay nMR to nQn output transition time +25 typ. 52 19 15 44 16 13 19 7 6 80 16 14 80 16 14 60 12 10 60 12 10 5 5 5 6.0 30 35 17 6 5 17 6 5 17 6 5 8 3 2 0 0 0 33 100 119 -40 to +85 max. min. 175 35 30 175 35 30 75 15 13 100 20 17 100 20 17 75 15 13 75 15 13 5 5 5 4.8 24 28 max. 220 44 37 220 44 37 95 19 16 120 24 20 120 24 20 90 18 15 90 18 15 5 5 5 4.0 20 24 -40 to +125 min. max. 265 53 45 265 53 45 110 22 19
74HC/HCT4015
TEST CONDITIONS UNIT VCC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6
ns
tPHL
ns
Fig.7
tTHL/ tTLH
ns
Fig.6
tW
clock pulse width HIGH or LOW master reset pulse width HIGH removal time nMR to nCP set-up time nD to nCP hold time nD to nCP maximum clock pulse frequency
ns
Fig.6
tW
ns
Fig.7
trem
ns
Fig.7
tsu
ns
Fig.8
th
ns
Fig.8
fmax
MHz
Fig.6
December 1990
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