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Part: 74HC574U
Category:
Logic
-> Flip-Flops
Description: 74HC/HCT574; Octal D-type Flip-flop; Positive Edge-trigger; 3-state
Company: Philips Semiconductors
Datasheet: Download 74HC574U datasheet File size : 230 kB
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
· The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications · The IC06 74HC/HCT/HCU/HCMOS Logic Package Information · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT574 Octal D-type flip-flop; positive edge-trigger; 3-state
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
FEATURES · 3-state non-inverting outputs for bus oriented applications · 8-bit positive edge-triggered register · Common 3-state output enable input · Independent register and 3-state buffer operation · Output capability: bus driver · ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT574 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT574 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and non-inverting 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops.
74HC/HCT574
The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The "574" is functionally identical to the "564", but has non-inverting outputs. The "574" is functionally identical to the "374", but has a different pinning.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay CP to Qn maximum clock frequency input capacitance power dissipation capacitance per flip-flop notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 14 123 3.5 22 HCT 15 76 3.5 25 ns MHz pF pF UNIT
December 1990
2
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
PIN DESCRIPTION PIN NO. 1 2, 3, 4, 5, 6, 7, 8, 9 10 11 19, 18, 17, 16, 15, 14, 13, 12 20 SYMBOL OE D0 to D7 GND CP Q0 to Q7 VCC NAME AND FUNCTION
74HC/HCT574
3-state output enable input (active LOW) data inputs ground (0 V) clock input (LOW-to-HIGH, edge-triggered) 3-state flip-flop outputs positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
FUNCTION TABLE OPERATING MODES load and read register load register and disable outputs Notes INPUTS OE L L H H CP Dn l h l h
74HC/HCT574
INTERNAL FLIP-FLOPS L H L H
OUTPUTS Q0 to Q7 L H Z Z
1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level l = LOW voltage level on set-up time prior to the LOW-to-HIGH CP transition Z = HIGH impedance OFF-state = LOW-to-HIGH clock transition
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990
4
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive edge-trigger; 3-state
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) 74HC SYMBOL PARAMETER min. tPHL/ tPLH propagation delay CP to Qn 3-state output enable time OE to Qn 3-state output disable time OE to Qn output transition time +25 typ. 47 17 14 44 16 13 39 14 11 14 5 4 80 16 14 60 12 10 5 5 5 6.0 30 35 14 5 4 6 2 2 0 0 0 37 112 133 max. 150 30 26 140 28 24 125 25 21 60 12 10 100 20 17 75 15 13 5 5 5 4.8 24 28 -40 to +85 min. max. 190 35 33 175 35 30 155 31 26 75 15 13 120 24 20 90 18 15 5 5 5 4.0 20 24 -40 to +125 min. max. 225 45 38 210 42 36 190 38 32 90 18 15 ns
74HC/HCT574
TEST CONDITIONS UNIT V CC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6
tPZH/ tPZL
ns
Fig.7
tPHZ/ tPLZ
ns
Fig.7
tTHL/ tTLH
ns
Fig.6
tW
clock pulse width HIGH or LOW set-up time Dn to CP hold time Dn to CP maximum clock pulse frequency
ns
Fig.6
tsu
ns
Fig.8
th
ns
Fig.8
fmax
MHz
Fig.6
December 1990
5
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