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Part: 74HC594N
Category:
Logic
-> Registers
-> Shift Registers
Description: 74HC/HCT594; 8-bit Shift Register With Output Register;; Package: SOT109-1 (SO16), SOT338-1 (SSOP16), SOT38-4 (DIP16)
Company: Philips Semiconductors
Datasheet: Download 74HC594N datasheet File size : 133 kB
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
· The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications · The IC06 74HC/HCT/HCU/HCMOS Logic Package Information · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT594 8-bit shift register with output register
Product specification File under Integrated Circuits, IC06 December 1991
Philips Semiconductors
Product specification
8-bit shift register with output register
FEATURES · Synchronous serial input and output · 8-bit parallel output · Shift and storage register have independent direct clear and clocks · 100 MHz (typ.) · Output capability: parallel outputs: bus driver serial outputs: standard · ICC category: MSI APPLICATIONS · Serial-to parallel data conversion · Remote control holding register DESCRIPTION
74HC/HCT594
The 74HC/HCT594 are high-speed, Si-gate CMOS devices, and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74HC/HCT594 contain an 8-bit, non-inverting, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks and direct overriding clears are provided on both the shift and storage registers. A serial output (Q7') is provided for cascading purposes. Both the shift and storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register will always be one count pulse ahead of the storage register.
QUICK REFERENCE DATA GND = 0 V: Tamb = 250 C; tr = tf = 6 ns. TYPICAL SYMBOL tPHL/tPLH PARAMETER propagation delay SHCP to Q7' STCP to Qn SHR to Qn STR to Qn fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + (CL × VCC2 × fo), where: fi = input frequency in MHz; fo = output frequency in MHz; (CL × VCC2 × fo) = sum of the outputs; CL = output load capacitance in pF; VCC = supply voltage in V. 2. For HC, the condition is VI = GND to VCC; for HCT, the condition is VI = GND to VCC - 1.5 V. ORDERING INFORMATION PACKAGES EXTENDED TYPE NUMBER PINS PC74HC/HCT594P PC74HC/HCT594T 16 16 PIN POSITION DIL SO MATERIAL plastic plastic CODE SOT38C, P SOT109A maximum clock frequency SHCP, STCP input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 13 13 11 11 100 3.5 84 15 15 14 14 100 3.5 89 ns ns ns ns MHz pF pF HCT UNIT
December 1991
2
Philips Semiconductors
Product specification
8-bit shift register with output register
PINNING SYMBOL Q0 to Q7 GND Q7' SHR SHCP STCP STR Ds VCC 8 9 10 11 12 13 14 16 PIN 15 & 1 to 7 parallel data outputs ground (0 V) serial data output shift register reset (active LOW) shift register clock input storage register clock input storage register reset active (LOW) serial data input supply voltage DESCRIPTION
74HC/HCT594
11
ge
12
ge
halfpage
SH CP ST CP Q7' Q0 Q1 Q2 14 DS Q3 Q4 Q5 Q6 SH R 10 ST R 13 Q7
ST R Q1 1 Q2 2 Q3 3 Q4 4 Q5 5 Q6 6 Q7 7 16 V CC 15 Q 0 14 D S 13 ST R DS ST CP SH R SH CP
13 12 10 11 14 R 1 SRG8 C1/ 1D
R2 C2
9 15 1 2 3 4 5 6 7
2D
15 1 2 3 4 5 6 7 9
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q7'
594
12 ST CP 11 SH CP 10 SH R 9 Q7'
GND 8
MBC318
MBC319
MBC322 - 1
Fig.1 Logic symbol.
Fig.2 Pin configuration.
Fig.3 IEC logic symbol.
December 1991
3
Philips Semiconductors
Product specification
8-bit shift register with output register
74HC/HCT594
handbook, halfpage
14 D S 11 SHCP 8-STAGE SHIFT REGISTER Q7' 12 ST CP 8-BIT STORAGE REGISTER
10 SH R 9
13 ST R
Q 0 Q1 Q 2 Q 3 Q4 Q 5 Q 6 Q 7 15 1 2 3 4 5 6 7
MBC320
Fig.4 Functional diagram.
FUNCTION TABLE INPUTS SHCP X X X STCP X X X SHR L X L H STR X L H X X X X H DS OUTPUTS FUNCTION Q7' L NC L Q6' Qn NC L L NC a LOW level on SHR only affects the shift registers. a LOW level on STR only affects the storage registers. empty shift register loaded into storage register. logic HIGH level shifted into shift register stage 0. Contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6') appears on the serial output (Q7'). contents of shift register stages (internal Qn') are transferred to the storage register and parallel output stages. contents of shift register shifted through. Previous contents of shift register transferred to the storage register and the parallel output stages.
X
H H
H H
X X
NC Q6n
Qn' Qn'
Note 1. H = HIGH voltage level L = LOW voltage level = LOW-to-HIGH transition NC = no change X = don't care.
December 1991
4
Philips Semiconductors
Product specification
8-bit shift register with output register
74HC/HCT594
handbook, full pagewidth
STAGE 0 DS D Q D
STAGES 1 TO 6 Q
STAGE 7 D Q Q7'
FFSH 0 CP R SHCP SH R
FFSH 7 CP R
D
Q
D CP
Q
FFST 0 CP R ST CP ST R
FFST 7 R
Q0
Q 1 Q 2 Q3 Q 4 Q 5 Q6
Q7
MBC321 - 1
Fig.5 Logic diagram.
handbook, fullP SH C pagewidth
DS ST CP SH R ST R Q0 Q1
Q6 Q7 Q 7'
MBC323 - 1
Fig.6 Timing diagram.
December 1991
5
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