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Details, datasheet, quote on part number:74HC597N
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| Part: | 74HC597N |
| Category: | Logic => Registers => Shift Registers |
| Description: | 74HC/HCT597; 8-bit Shift Register With Input Flip-flops;; Package: SOT109-1 (SO16), SOT338-1 (SSOP16), SOT38-4 (DIP16), SOT403-1 (TSSOP16) |
| Company: | Philips Semiconductors |
| Datasheet: | Download 74HC597N datasheet File size : 82 kB |
| Request For quote: | Find where to buy 74HC597N
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Datasheet text preview:
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
· The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications · The IC06 74HC/HCT/HCU/HCMOS Logic Package Information · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT597 8-bit shift register with input flip-flops
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
8-bit shift register with input flip-flops
FEATURES · 8-bit parallel storage register inputs · Shift register has direct overriding load and clear · Output capability: standard · ICC category: MSI GENERAL DESCRIPTION
74HC/HCT597
The 74HC/HCT597 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT597 consist each of an 8-bit storage register feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and the shift register have positive edge-triggered clocks. The shift register also has direct load (from storage) and clear inputs.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay SHCP to Q STCP to Q PL to Q fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". maximum clock frequency SHCP input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 17 25 21 96 3.5 29 20 29 26 83 3.5 32 ns ns ns MHz pF pF HCT UNIT
December 1990
2
Philips Semiconductors
Product specification
8-bit shift register with input flip-flops
PIN DESCRIPTION PIN NO. 8 9 10 11 12 13 14 15, 1, 2, 3, 4, 5, 6, 7 16 SYMBOL GND Q MR SHCP STCP PL DS D0 to D7 VCC NAME AND FUNCTION ground (0 V) serial data output asynchronous reset input (active LOW)
74HC/HCT597
shift clock input (LOW-to-HIGH, edge-triggered) storage clock input (LOW-to-HIGH, edge-triggered) parallel load input (active LOW) serial data input parallel data inputs positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
8-bit shift register with input flip-flops
74HC/HCT597
Fig.4 Functional diagram.
FUNCTION TABLE STCP no clock edge X X X Notes 1. H L X = HIGH voltage level = LOW voltage level = don't care = LOW-to-HIGH CP transition SHCP X X X X X PL X L L L H H MR X H H L L H FUNCTION data loaded to input latches data loaded from inputs to shift register data transferred from input flip-flops to shift register invalid logic, state of shift register indeterminate when signals removed shift register cleared shift register clocked Qn = Qn-1, Q0 = DS
December 1990
4
Philips Semiconductors
Product specification
8-bit shift register with input flip-flops
74HC/HCT597
Fig.5 Logic diagram.
December 1990
5
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