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Part: 74HC6323A
Category:
Logic
-> Counters
Description: 74HC/HCT6323A; Programmable Ripple Counter With Oscillator; 3-state
Company: Philips Semiconductors
Datasheet: Download 74HC6323A datasheet File size : 133 kB
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Datasheet text preview:
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
· The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications · The IC06 74HC/HCT/HCU/HCMOS Logic Package Information · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT6323A Programmable ripple counter with oscillator; 3-state
Product specification Supersedes data of December 1990 File under Integrated Circuits, IC06 September 1993
Philips Semiconductors
Product specification
Programmable ripple counter with oscillator; 3-state
FEATURES · 8-pin space saving package · Programmable 3-stage ripple counter · Suitable for over-tone crystal application up to 50 MHz (VCC = 5 V ± 10%) · 3-state output buffer · Two internal capacitors · Recommended operating range for use with third overtone crystals 3 to 6 V · Oscillator stop function (MR) · Output capability: bus driver (15 LSTTL) · ICC category: MSI. APPLICATIONS · Control counters · Timers · Frequency dividers · Time-delay circuits · CIO (Compact Integrated Oscillator) · Third-overtone crystal operation. Notes GENERAL DESCRIPTION The HC/HCT6323A are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no. 7A. The HC/HCT6323A are oscillators designed for quartz crystal combined with a programmable 3-state counter, a 3-state output buffer and an overriding asynchronous master reset (MR). With the two select inputs S1 and S2 the counter can be switched in the divide-by-1, 2, 4 or 8 mode. If left floating the clock is divided by 8. The oscillator is designed to operate either in the fundamental or third overtone mode depending on the crystal and external components applied. On-chip September 1993 CPD SYMBOL tPHL/tPLH PARAMETER propagation delay X1 to OUT (S1 = S2 = LOW) maximum clock frequency input capacitance except X1 and X2 power dissipation capacitance per package capacitors minimize external component count for third overtone crystal applications. The oscillator may be replaced by an external clock signal at input X1. In this event the other oscillator pin (X2) must be floating. The counter advances on the negative-going transition of X1. A LOW level on MR resets the counter, stops the oscillator QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
74HC/HCT6323A
and sets the output buffer in the 3-state condition. MR can be left floating since an internal pull-up resistor will make the MR inactive. In the HCT version, the MR input and the two mode select pins S1 and S2 are TTL compatible, but the X1 input has CMOS input switching levels and may be driven by a TTL output using a pull-up resistor connected to VCC.
TYP. CONDITIONS HC CL = 15 pF; VCC = 5 V 17 HCT 17 ns UNIT
fmax CI
90 3.5 +1; notes 1 and 2 +2; notes 1 and 2 +4; notes 1 and 2 +8; notes 1 and 2 54 42 36 33
90 3.5 54 42 36 33
MHz pF pF pF pF pF
1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = (CPD x VCC2 x fi) + (CL + VCC2 x fo) + (Ipull-up x VCC) where: fi = input frequency in MHz; fo = output frequency in MHz. VCC = supply voltage in V; CL = output load capacitance in pF. Ipull-up = pull-up currents in µA. 2. For HC and HCT an external clock is applied to X1 with: tr = tf 6 ns, Vi is GND to VCC, MR = HIGH Ipull-up is the summation of -II (µA) of S1 and S2 inputs at the LOW state. ORDERING INFORMATION EXTENDED TYPE NUMBER 74HC/HCT6323AD PACKAGE PINS 8 PIN POSITION SO MATERIAL plastic CODE SOT96
2
Philips Semiconductors
Product specification
Programmable ripple counter with oscillator; 3-state
PINNING SYMBOL OUT S1 - S2 GND MR X2 X1 VCC PIN 1 3, 2 4 5 6 7 8 DESCRIPTION counter output mode select inputs for divide by 1, 2, 4 or 8 ground (0 V) master reset (active LOW) oscillator pin clock input/oscillator pin positive supply S1 0 0 1 1 FUNCTION TABLE INPUTS S2 0 1 0 1
74HC/HCT6323A
OUTPUTS OUT fi fi/2 fi/4 fi/8
6
handbook, halfpage handbook, halfpage
OUT S2 S1 GND
1 2
8 7
VCC X1 X2 MR 7 5
X1 CP MR 3 2 CD S1 S2
X2
6323A
3 4
MBA343
6 5
OUT
MBA344
1
Fig.1 Pin configuration.
Fig.2 IEC logic symbol.
6
handbook, full pagewidth
X2 7 X1 CP MR
MBA350
3 - STAGE BINARY COUNTER AND DECODER S1 3 S2 2 OUT 1
5
CD
Fig.3 Functional diagram.
September 1993
3
Philips Semiconductors
Product specification
Programmable ripple counter with oscillator; 3-state
74HC/HCT6323A
handbook, full pagewidth
X2 X1 7 pF VCC 7 pF CP Q
(1) (1)
CP Q FF R
CP Q FF R
FF R
V CC
DECODER VCC VCC MR S1 S2 VCC OUT
MBA349
Internal capacitors typical 7 pF each. Including stray capacitors on pin X1 and X2, total capacitance will be typical 12 pF per pin.
Fig.4 Logic diagram.
September 1993
4
Philips Semiconductors
Product specification
Programmable ripple counter with oscillator; 3-state
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: non-standard; bus driver (except for X2) ICC category: MSI. Voltages are referenced to GND (ground = 0 V). DC CHARACTERISTICS FOR 74HC Tamb(°C) SYMBOL PARAMETER MIN VIH HIGH level input voltage MR, X1 input LOW level input voltage MR, X1 input HIGH level output voltage X2 output 1.5 3.15 4.2 - - - 3.98 5.48 3.98 5.48 1.9 4.4 5.9 1.9 4.4 5.9 VOH HIGH level output voltage OUT HIGH level output voltage OUT LOW level output voltage X2 output 1.9 4.4 5.9 3.98 5.48 - - - - - VOL LOW level output voltage OUT - - - 25 TYP MAX 1.2 2.4 3.2 0.8 2.1 2.8 - - - - 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 - - - - 0 0 0 0 0 0 - - - 0.5 1.35 1.80 - - - - - - - - - - - - - - - 0.26 0.26 0.1 0.1 0.1 0.1 0.1 0.1 -40 to 85 MIN 1.5 3.15 4.2 - - - 3.84 5.34 3.84 5.34 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 3.84 5.34 - - - - - - - - - - - 0.5 1.35 1.8 - - - - - - - - - - - - - - - 0.33 0.33 0.1 0.1 0.1 0.1 0.1 0.1 -40 to 125 UNIT V CC (V) MAX MIN MAX 1.50 - 3.15 - 4.20 - - - - 3.7 5.2 3.7 5.2 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 3.7 5.2 - - - - - - - - 0.5 1.35 1.8 - - - - - - - - - - - - - - - 0.4 0.4 0.1 0.1 0.1 0.1 0.1 0.1 V V V V V V V V V V V V V V V V V V V V V V V V V V V V V 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0
74HC/HCT6323A
TEST CONDITION VI OTHER
VIL
VOH
X1 = GND and MR = VCC X1 = VCC and MR = GND X1 = GND and MR = VCC X1 = VCC and MR = GND VIH or VIL
IO = -2.6 mA IO = -3.3 mA IO = -2.6 mA IO = -3.3 mA -IO = 20 µA IO = -20 µA IO = -20 µA IO = -20 µA IO = -20 µA IO = -20 µA IO = -20 µA IO = -20 µA IO = -20 µA IO = -6 mA IO = -7.8 mA IO = 2.6 mA IO = 3.3 mA IO = 20 µA IO = 20 µA IO = 20 µA IO = 20 µA IO = 20 µA IO = 20 µA
VOH
VIH or VIL
VOL
X1 = VCC and MR = VCC X1 = VCC and MR = VCC VIH or VIL
September 1993
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