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Part: 74HCT4017
Category:
Logic
-> Counters
Description: 74HC/HCT4017; Johnson Decade Counter With 10 Decoded Outputs
Company: Philips Semiconductors
Datasheet: Download 74HCT4017 datasheet File size : 263 kB
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
· The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications · The IC06 74HC/HCT/HCU/HCMOS Logic Package Information · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4017 Johnson decade counter with 10 decoded outputs
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
FEATURES · Output capability: standard · ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4017 are high-speed Si-gate CMOS devices and are pin compatible with the "4017" of the "4000B" series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4017 are 5-stage Johnson decade counters with 10 decoded active HIGH outputs (Q0 to Q9), an active LOW output from the most significant flip-flop (Q5-9), active HIGH and active LOW clock inputs (CP0 and
74HC/HCT4017
CP1) and an overriding asynchronous master reset input (MR). The counter is advanced by either a LOW-to-HIGH transition at CP0 while CP1 is LOW or a HIGH-to-LOW transition at CP1 while CP0 is HIGH (see also function table). When cascading counters, the Q5-9 output, which is LOW while the counter is in states 5, 6, 7, 8 and 9, can be used to drive the CP0 input of the next counter. A HIGH on MR resets the counter to zero (Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW) independent of the clock inputs (CP0 and CP1). Automatic code correction of the counter is provided by an internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi+ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay CP0, CP1 to Qn maximum clock frequency input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 20 77 3.5 35 HCT 21 67 3.5 36 ns MHz pF pF UNIT
December 1990
2
Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
PIN DESCRIPTION PIN NO. 3, 2, 4, 7, 10, 1, 5, 6, 9, 11 8 12 13 14 15 16 SYMBOL Q0 to Q9 GND Q5-9 CP1 CP0 MR VCC NAME AND FUNCTION decoded outputs ground (0 V) carry output (active LOW)
74HC/HCT4017
clock input (HIGH-to-LOW, edge-triggered) clock input (LOW-to-HIGH, edge-triggered) master reset input (active HIGH) positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
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Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
74HC/HCT4017
Fig.4 Functional diagram.
FUNCTION TABLE MR H L L L L L L Notes 1. H = HIGH voltage level L = LOW voltage level X = don't care = LOW-to-HIGH clock transition = HIGH-to-LOW clock transition CP0 X H L X H CP1 X L X H L OPERATION Q0 = Q5-9 = H; Q1 to Q9 = L counter advances counter advances no change no change no change no change
December 1990
4
Philips Semiconductors
Product specification
Johnson decade counter with 10 decoded outputs
74HC/HCT4017
Fig.5 Logic diagram.
Fig.6 Timing diagram.
December 1990
5
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