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Details, datasheet, quote on part number:74HCT7030N
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| Part: | 74HCT7030N |
| Category: | Logic => FIFOs => Registers |
| Description: | 74HC/HCT7030; 9-bit X 64-word Fifo Register; 3-state;; Package: SOT117-1 (DIP28), SOT136-1 (SO28) |
| Company: | Philips Semiconductors |
| Datasheet: | Download 74HCT7030N datasheet File size : 170 kB |
| Request For quote: | Find where to buy 74HCT7030N
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Datasheet text preview:
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
· The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications · The IC06 74HC/HCT/HCU/HCMOS Logic Package Information · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7030 9-bit x 64-word FIFO register; 3-state
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
9-bit x 64-word FIFO register; 3-state
FEATURES · Synchronous or asynchronous operation · 3-state outputs · Master-reset input to clear control functions · 33 MHz (typ.) shift-in, shift-out rates with or without flags · Very low power consumption · Cascadable to 25 MHz (typ.) · Readily expandable in word and bit dimensions · Pinning arranged for easy board layout: input pins directly opposite output pins · Output capability: standard · ICC category: LSI GENERAL DESCRIPTION The 74HC/HCT7030 are high-speed Si-gate CMOS devices specified in compliance with JEDEC standard no. 7A. The 74HC/HCT7030 is an expandable, First-In First-Out (FIFO) memory organized as 64 words by 9 bits. A 33 MHz data-rate makes it ideal for high-speed applications. Even at high frequencies, the ICC dynamic is very low (fmax = 18 MHz; VCC = 5 V produces a dynamic ICC of 80 mA). If the device is not continuously operating at fmax, then ICC will decrease proportionally. With separate controls for shift-in (SI) and shift-out (SO), reading and writing operations are completely independent, allowing synchronous and asynchronous data transfers. Additional controls include a master-reset input (MR) and an output enable input (OE). Flags for data-in-ready (DIR) and data-out-ready (DOR) indicate the status of the device. Devices can be interconnected easily to expand word and bit dimensions. All output pins are directly opposite the corresponding input pins thus simplifying board layout in expanded applications. INPUTS AND OUTPUTS Data inputs (D0 to D8) As there is no weighting of the inputs, any input can be assigned as the MSB. The size of the FIFO memory can be reduced from the 9 × 64 configuration, i.e. 8 × 64, 7 × 64, down to 1 × 64, by tying unused data input pins to VCC or GND. Master-reset (MR) Data outputs (Q0 to Q8)
74HC/HCT7030
As there is no weighting of the outputs, any output can be assigned as the MSB. The size of the FIFO memory can be reduced from the 9 × 64 configuration as described for data inputs. In a reduced format, the unused data output pins must be left open circuit.
When MR is LOW, the control functions within the FIFO are cleared, and data content is declared invalid. The data-in-ready (DIR) flag is set HIGH and the data-out-ready (DOR) flag is set LOW. The output stage remains in the state of the last word that was shifted out, or in the random state existing at power-up. Status flag outputs (DIR, DOR) Indication of the status of the FIFO is given by two status flags, data-in-ready (DIR) and data-out-ready (DOR): DIR DIR = HIGH indicates the input stage is empty and ready to accept valid data = LOW indicates that the FIFO is full or that a previous shift-in operation is not complete (busy)
DOR = HIGH assures valid data is present at the outputs Q0 to Q8 (does not indicate that new data is awaiting transfer into the output stage) DOR = LOW indicates the output stage is busy or there is no valid data Shift-in control (SI) Data is loaded into the input stage on a LOW-to-HIGH transition of SI. A HIGH-to-LOW transition triggers an automatic data transfer process (ripple through). If SI is held HIGH during reset, data will be loaded at the rising edge of the MR signal. Shift-out control (SO) A LOW-to-HIGH transition of SO causes the DOR flags to go LOW. A HIGH-to-LOW transition of SO causes upstream data to move into the output stage, and empty locations to move towards the input stage (bubble-up). Output enable (OE) The outputs Q0 to Q8 are enabled when OE = LOW. When OE = HIGH the outputs are in the high impedance OFF-state.
December 1990
2
Philips Semiconductors
Product specification
9-bit x 64-word FIFO register; 3-state
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
74HC/HCT7030
TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay MR to DIR and DOR SO to Qn fmax CI CP Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". maximum clock frequency SI and SO input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 21 36 33 3.5 660 26 40 29 3.5 660 ns ns MHz pF pF HCT UNIT
December 1990
3
Philips Semiconductors
Product specification
9-bit x 64-word FIFO register; 3-state
PIN DESCRIPTION PIN NO. 1, 2, 14 3 4 5, 6, 7, 8, 9, 10, 11, 12, 13 15 24, 23, 22, 21, 20, 19, 18, 17, 16 25 26 27 28 Note SYMBOL GND DIR SI D0 to D8 OE Q0 to Q8 DOR SO MR VCC NAME AND FUNCTION ground (0 V) data-in-ready output
74HC/HCT7030
shift-in input (LOW-to-HIGH, edge-triggered) parallel data inputs output enable input (active LOW) 3-state parallel data outputs data-out-ready output shift-out input (HIGH-to-LOW, edge-triggered) asynchronous master-reset input (active LOW) positive supply voltage
1. Pin 14 must be connected to GND. Pins 1 and 2 can be left floating or connected to GND, however it is not allowed to let current flow in either direction between pins 1, 2 and 14.
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
4
Philips Semiconductors
Product specification
9-bit x 64-word FIFO register; 3-state
74HC/HCT7030
Fig.4 Functional diagram.
APPLICATIONS · High-speed disc or tape controller · Video timebase correction · A/D output buffers · Voice synthesis · Input/output formatter for digital filters and FFTs · Bit-rate smoothing
December 1990
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