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Details, datasheet, quote on part number:74HCT7080
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Datasheet text preview:
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
· The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications · The IC06 74HC/HCT/HCU/HCMOS Logic Package Information · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7080 16-bit even/odd parity generator/checker
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
16-bit even/odd parity generator/checker
FEATURES · Word-length easily expanded by cascading · Generates either even or odd parity for 16-data bits · Output capability: standard · ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT7080 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
74HC/HCT7080
The 74HC/HCT7080 are 16-bit parity generators or checkers commonly used to detect errors in high-speed data transmission or data retrieval systems. The even and odd parity output is available for generating or checking even/odd parity up to 16-bits. The even/odd parity output (E/O) is HIGH when an even number of data inputs (I0 to I15) are HIGH and the cascade/even-odd-changing input (X) is HIGH. Expansion to larger word sizes is accomplished by connecting the even/odd parity output (E/O) to the cascade/even-odd-changing input (X) of the final stage.
TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay In to E/O X to E/O CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + (CL ×VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 29 12 3.5 24 32 15 3.5 25 ns ns pF pF HCT UNIT
December 1990
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Philips Semiconductors
Product specification
16-bit even/odd parity generator/checker
PIN DESCRIPTION PIN NO. 1 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18 10 19 20 SYMBOL X I0 to I15 GND E/O VCC
74HC/HCT7080
NAME AND FUNCTION cascade/even-odd-changing input data inputs ground (0 V) even/odd parity output positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
16-bit even/odd parity generator/checker
74HC/HCT7080
Fig.4 Functional diagram.
FUNCTION TABLE INPUTS In =E E Notes 1. H = HIGH voltage level L = LOW voltage level E = even X H L H L OUTPUTS E/O H L L H Fig.5 Logic diagram.
December 1990
4
Philips Semiconductors
Product specification
16-bit even/odd parity generator/checker
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) 74HC SYMBOL PARAMETER min. tPHL/ tPLH propagation delay In to E/O propagation delay X to E/O output transition time +25 typ. 91 33 26 41 15 12 19 7 6 -40 to +85 -40 to +125 max. 420 84 71 225 45 38 110 22 19 ns
74HC/HCT7080
TEST CONDITIONS UNIT V CC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.7
max. min. max. min. 280 56 48 150 30 26 75 15 13 350 70 60 190 38 33 95 19 16
tPHL/ tPLH
ns
Fig.6
tTHL/ tTLH
ns
Figs 6 and 7
December 1990
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