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Details, datasheet, quote on part number:74HCT7132
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| Part: | 74HCT7132 |
| Category: | Logic |
| Description: | 74HC/HCT7132; Quad Precision Adjustable Schmitt-trigger / Comparator With Output Latches; 3-state |
| Company: | Philips Semiconductors |
| Datasheet: | Download 74HCT7132 datasheet File size : 111 kB |
| Request For quote: | Find where to buy 74HCT7132
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Datasheet text preview:
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
· The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications · The IC06 74HC/HCT/HCU/HCMOS Logic Package Information · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7132 Quad precision adjustable Schmitt-trigger / comparator with output latches; 3-state
Product specification File under Integrated Circuits, IC06 September 1993
Philips Semiconductors
Product specification
Quad precision adjustable Schmitt-trigger / comparator with output latches; 3-state
FEATURES · Precision inputs · 2 operation modes: PAST and comparator · In PAST mode: Inverting outputs in view of the precision oscillator application · In comparator mode: Non-inverting outputs to simplify the design of an external hysteresis network · 3-state outputs for bus oriented applications · Output capability: Bus driver · ICC category: MSI APPLICATIONS · Precision oscillators · Signal reconditioning QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns SYMBOL VrH VrL Vt CPD PARAMETER High trip level reference level Low trip level DC inaccuracy power dissipation capacitance per function CONDITIONS PAST mode; VCC = 3 to 6 V Comparator mode; VCC = 3 to 6 V PAST mode; VCC = 3 to 6 V VCC = 3 to 6 V VCC = 5 V PAST mode Comparator mode Pd trmin/tfmin tPHL/tPLH Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + CL × VCC2 × fo where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacity in pF; VCC = supply voltage in V. September 1993 2 Total DC power dissipation Comparator mode; VCC = 4.5 V; VrL = VINn = 0 V; VrH = 2.25 V Minimum rise and fall time for optimum operation propagation delay Vinn to Q PAST mode; VCC = 4.5 V; VrH = 3 V; VrL = 1.5 V PAST mode; VCC = 4.5 V · Level conversion · Process control (temperature, pressure, power e.g.) · Accurate level detectors · Time delays · Overvoltage, overcurrent protection · Bargraph display with LED's · Battery charge control · Analog to digital conversion DESCRIPTION The 74HC/HCT7132 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT7132 contain 4 comparators with two common
74HC/HCT7132
reference inputs VrH and VrL and four separate signal inputs Vin0 to Vin3. The circuits can be applied in two modes: 1. The PAST (precision adjustable Schmitt-trigger) mode at which a voltage level equal to the wanted VT+ must be applied to the VrH input and a voltage level equal to the wanted VT- to the VrL input. 2. The comparator mode at which the VrL input must be connected to GND and the VrH input is the active reference level input. In this mode a few resistors must be added to achieve a small hysteresis in order to avoid oscillations. The operation in both modes will be further explained by means of the logic diagram of Fig.5.
TYPICAL 1.15 to VCC - 1.2 0.6 to VCC 1.10 to VCC - 1.25 ±20 100 30 8 180 40/60
UNIT V V V mV pF pF mW ns ns
Philips Semiconductors
Product specification
Quad precision adjustable Schmitt-trigger / comparator with output latches; 3-state
ORDERING INFORMATION PACKAGE TYPE NUMBER PINS 74HC/HCT7132P 74HC/HCT7132T PINNING PIN 1, 6, 8, 13 2 3, 5, 10, 12 4 7 9 11 14 OE Vin0 to Vin3 VrL GND LE VrH VCC SYMBOL Q0 to Q3 14 14 PIN POSITION DIL SO
74HC/HCT7132
MATERIAL plastic plastic
CODE SOT27 SOT108
NAME AND FUNCTION 3-state latch outputs 3-state output enable input (active LOW) signal inputs low reference voltage input ground (0 V) latch enable input (active HIGH) high reference voltage input positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
September 1993
3
Philips Semiconductors
Product specification
Quad precision adjustable Schmitt-trigger / comparator with output latches; 3-state
Table 1 Function table for PAST mode LE L L L L LE L L L H X L L L L H L L L L OE L H H Qt-1 Z OE H H L L Qn Qn The latch
74HC/HCT7132
Vinn (rising edge) Vinn Vinn > VrH Vinn > VHH Vinn (falling edge) VHH > Vinn > VrL VLL < Vinn < VrL Vinn < VLL Vinn = X Vinn = X Note
The output information can be stored in a latch on activating the LE input. In the PAST mode this latch is also used to control the reference input of the comparator which is either connected to the VrH input via SW1 or to the VrL input via SW2. In case of the comparator mode the reference input is always connected to the VrH input. This is done by means of an AND gate. The exclusive OR gate By means of this function the output stage is switched between inverting and non-inverting. In the PAST mode the inverting output of the mode selector is "1" so the exclusive OR is inverting. In the comparator mode this output is "0" so the exclusive OR is non-inverting. The operation in the PAST mode The operation in the PAST mode will be further outlined with the aid of Fig.5 and 9. and Table 1. When the level of VINn is 0 V the power of the comparator is switched OFF and the output circuit is controlled by the digital detector which output is LOW in that situation. So the output of the transparent latch is LOW. As the output stage is inverting now Qn is HIGH. In this condition the reference input of the comparator is connected to the +VrH input. When starting from 0 V the level at Vinn is increased, at about the VLL level (1 V) the DC power of the comparator is switched ON. The control of the output circuit is switched over from the digital detector output to the comparator output, when after a delay the voltage at this node is stabilised. During this operation the output level of the latch output remains LOW and the level of Qn HIGH. When the level at Vinn reaches the VrH level the output level of the comparator turns to HIGH and so the output level of the transparent latch. The level at Qn turns to LOW. In this instant the reference input of the comparator is switched over from VrH to VrL leaving the output voltage at Qn constant. When the level at Vinn reaches the VHH level ( VCC - 1 V) the DC power of the comparator is switched OFF. The control of the output circuit is switched over from the comparator output to the digital detector output which voltage level is HIGH in this situation. During this action the level at Qn remains LOW. When the level at the Vinn input is decreased starting at VCC level, at the VHH level (VCC - 1 V) the power of the comparator will be switched on again. The control of the output circuit is switched over from the digital detector output to the comparator output when after a delay the voltage at this node is stabilised. As the comparator output level is HIGH in this situation the output level of the latch remains HIGH and the Qn output LOW. When the level at Vinn reaches the VrL level the 4
1. H = HIGH voltage level L = LOW voltage level Z = high impedance OFF-state X = don't care Qt-1 = initial state DETAILED DESCRIPTION The mode selector. See Fig.5 for logic diagram. The circuit can be applied in two modes that are selected by the mode selector on bases of the level on the VrL input. When the level on this input is in the operating area of the PAST mode (VrL > 1 V) the true output of the mode detector is "0" which means that the PAST mode is selected. When the VrL input is at GND level the true output of the mode detector is "1" by which the comparator mode is selected. This mode needs only one reference input being the VrH input. The Power-on Detector The power-on detector selects a window typically between VINn = 1 V and VINn = VCC - 1 V in which in case of the PAST mode the power of the analog part (comparator) is switched on. When operating in the comparator mode the power is always switched on by means of an OR gate. The digital detector The digital detector is a Flip-Flop which output is set to LOW when VINn VCC - 1 V. This detector controls the output stage in the cases that the power of the comparator is switched off. This is performed by means of the switches SW3 and SW4.
September 1993
Philips Semiconductors
Product specification
Quad precision adjustable Schmitt-trigger / comparator with output latches; 3-state
output level of the comparator turns to LOW and so the output level of the transparent latch. The level at Qn turns to HIGH. In this instant the reference input of the comparator is switched over from VrL to VrH leaving the output voltage at Qn constant. When the level at Vinn reaches about 1 V the DC power of the comparator is switched OFF again. The control of the output circuit is switched over from the comparator output to the digital detector output which voltage level is LOW in this situation. During this action the level at Qn remains HIGH. The function of the circuit is a Schmitt-trigger of which the VT+ and VT- levels can be set at the VrH and VrL inputs. These levels can be varied from 1 V up to VCC - 1 V. so the maximum obtainable hysteresis is VCC - 2 V. The on-and off switching of the power and the stabilization of the comparator needs time, therefore the minimum applicable rise- and fall time of the input signal are limited when the maximum accuracy is required. When during the rise time of the input signal the input level has past the VLL level, the power starts to switch on. Only when the comparator is stable at the moment that the input signal passes the VrH level the comparator has its true delay and its optimal accuracy. When the VrH level is passed before the comparator is stable an extra delay occurs due to the switching of the power and the accuracy of the comparator is less. At the positive going edge, this extra delay depends on the difference between VLL and VrH and the rise time of the signal. This is shown in Fig.8, where by means of curves A and B tPHL is plotted at VrH is 1.15 V and 2.25 V respectively and VCC = 4.5 V. As with curve a VrH is very close to VLL the part of the input edge that is available for switching the power on is very small. This causes that only at a rise time > 500 ns/V the delay will be equal to the true delay of the comparator. At VrH = 2.25 V this situation is reached already at a rise time of 120 ns/V. At a very short rise time, the major part of the propagation delay is due to the switching time of the power. At the negative going edge, the power is switched on when the level VHH is passed so the extra delay depends on the difference between VHH and VrL and the fall time of the signal. This situation is referred to with curves C and D where tPLH is drawn against the fall time of the input signal. With curve C VrL is 3.25 V which is on the edge of the operating region. Curve D corresponds with a VrL value of 2.25 V. For linear input edges the recommended minimum rise time at VCC = 4.5 V or 6 V is 100 ns/V and at VCC = 3 V, 300 ns/V. For non-linear input signals, during the rising edge there must be a delay between the time at which the VLL level is passed and the time at which the VrH level is passed. This delay will be dependent on the VCC level and the amplitude of the overdrive of VLL. There is no limitation on the signal slope during the passing of the levels. For the same reasons, during the falling edge there September 1993 5
74HC/HCT7132
must be a delay between the time at which the VHH level is passed and the time at which the VrL level is passed. A possible application of the circuit is as precision oscillator see Fig.6. The operating frequency is: 1 f = ----------------------------------------------------------tR C + 2 × ( tP L H + tP H L) VC C Vr L where t R C = 2 × In ------------------------- × R C VC C Vr H The operation in the comparator mode The IC can be applied as a comparator by connecting the VrL input to GND and adjusting the level at VrH to the wanted detection level see Fig.7. In this mode the DC power of the comparator is always on and the output stage is set to non-inverting. The function table for this operation mode is given in table 2. Table 2 Function table for Comparator mode LE L L H X L L L H OE L H Qn-1 Z Qn
INPUT Vinn Vref Vinn = X Vinn = X Notes
1. H = HIGH voltage level L = LOW voltage level Z = high impedance OFF-state X = don't care The fact that the power is always on offers the feature of a more extended operation region of the VrH input voltage which is at a VCC of 4.5 V from 1.1 V up to 4.2 V see also Fig.12. A hysteresis of about 50 mV is required to overcome oscillations. This has to be performed by means of a few external resistors. The DC power in this operation mode at VCC = 4.5 V is typical 2 mW per function. A curve showing tPD as a function of the overdrive is given in Fig.11. A possible diagram for a bargraph display is shown in Fig.10.
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