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Part: 74HC/HCT166
Category:
Logic
-> Registers
-> CMOS/BiCMOS->HC/HCT Family
Description: 8-bit Parallel-in/serial-out Shift Register
Company: Philips Semiconductors
Datasheet: Download 74HC/HCT166 datasheet File size : 156 kB
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
· The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications · The IC06 74HC/HCT/HCU/HCMOS Logic Package Information · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT166 8-bit parallel-in/serial-out shift register
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
FEATURES · Synchronous parallel-to-serial applications · Synchronous serial data input for easy expansion · Clock enable for "do nothing" mode · Asynchronous master reset · For asynchronous parallel data load see "165" · Output capability: standard · ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT166 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT166 are 8-bit shift registers which have a fully synchronous serial or parallel data entry selected by
74HC/HCT166
an active LOW parallel enable (PE) input. When PE is LOW one set-up time prior to the LOW-to-HIGH clock transition, parallel data is entered into the register. When PE is HIGH, data is entered into the internal bit position Q0 from serial data input (Ds), and the remaining bits are shifted one place to the right (Q0 Q1 Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by tying the Q7 output to the Ds input of the succeeding stage. The clock input is a gated-OR structure which allows one input to be used as an active LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE should only take place while CP is HIGH for predictable operation. A LOW on the master reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all bit positions to a LOW state.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay CP to Q7 MR to Q7 maximum clock frequency input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 15 14 63 3.5 41 20 19 50 3.5 41 ns ns MHz pF pF HCT UNIT
fmax CI CPD Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information".
December 1990
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Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
PIN DESCRIPTION PIN NO. 1 2, 3, 4, 5, 10, 11, 12, 14 6 7 8 9 13 15 16 SYMBOL Ds D0 to D7 CE CP GND MR Q7 PE VCC NAME AND FUNCTION serial data input parallel data inputs clock enable input (active LOW)
74HC/HCT166
clock input (LOW-to-HIGH edge-triggered) ground (0 V) asynchronous master reset (active LOW) serial output from the last stage parallel enable input (active LOW) positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT166
Fig.4 Functional diagram.
FUNCTION TABLE INPUTS OPERATING MODES PE parallel load serial shift hold "do nothing" Notes 1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition X = don't care = LOW-to-HIGH CP transition I I h h X I I I I h CE X CP X X I h X DS D0-D7 I-I h-h X-X X-X X-X L H L H q0 Qn REGISTER Q0 Q1-Q6 L-L H-H q0 - q5 q0 - q5 q 1 - q6 OUTPUT Q7 L H q6 q6 q7
December 1990
4
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT166
Fig.5 Logic diagram.
Fig.6 Typical clear, shift, load, inhibit, and shift sequences.
December 1990
5
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