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Details, datasheet, quote on part number:74HC/HCT181
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INTEGRATED CIRCUITS
DATA SHEET
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· The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications · The IC06 74HC/HCT/HCU/HCMOS Logic Package Information · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT181 4-bit arithmetic logic unit
Product specification Supersedes data of September 1993 File under Integrated Circuits, IC06 1998 Jun 10
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
FEATURES · Full carry look-ahead for high-speed arithmetic operation on long words · Provides 16 arithmetic operations: add, subtract, compare, double, plus 12 others · Provides all 16 logic operations of two variables: EXCLUSIVE-OR, compare, AND, NAND, NOR, OR plus 10 other logic operations · Output capability: · ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT181 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT181 are 4-bit high-speed parallel Arithmetic Logic Units (ALU). Controlled by the four function select inputs (S0 to S3) and the mode control input (M), they can perform all the 16 possible logic operations or 16 different arithmetic operations on active HIGH or active LOW operands (see function table). When the mode control input (M) is HIGH, all internal carries are inhibited and the device3 performs logic operations on the individual bits as listed. When M is LOW, the carries are enabled and the "181" performs arithmetic operations on the two 4-bit words. The "181" incorporates full internal carry look-ahead and provides for either ripple carry between devices using the Cn+4 output, or for carry look-ahead between packages using the carry propagation (P) and carry generate (G) signals. P and G are not affected by carry in. ORDERING INFORMATION TYPE NUMBER 74HC181N3; 74HCT181N3 74HC181N; 74HCT181N 74HC181D; 74HCT181D PACKAGE NAME DIP24 DIP24 SO24 DESCRIPTION plastic dual in-line package; 24 leads (300 mil) plastic dual in-line package; 24 leads (600 mil) plastic small outline package; 24 leads; body width 7.5 mm standard, A=B open drain
74HC/HCT181
When speed requirements are not stringent, it can be used in a simple ripple carry mode by connecting the carry output (Cn+4) signal to the carry input (Cn) of the next unit. For high-speed operation the device is used in conjunction with the "182" carry look-ahead circuit. One carry look-ahead package is required for each group of four "181" devices. Carry look-ahead can be provided at various levels and offers high-speed capability over extremely long word lengths. The comparator output (A=B) of the device goes HIGH when all four function outputs (F0 to F3) are HIGH and can be used to indicate logic equivalence over 4 bits when the unit is in the subtract mode. A=B is an open collector output and can be wired-AND with other A=B outputs to give a comparison for more than 4 bits. The open drain output A=B should be used with an external pull-up resistor in order to establish a logic HIGH level. The A=B signal can also be used with the Cn+4 signal to indicate A > B and A < B. The function table lists the arithmetic operations that are performed without a carry in. An incoming carry adds a one to each operation. Thus, select code LHHL generates A minus B minus 1 (2s complement notation) without a carry in and generates A minus B when a carry is applied. Because subtraction is actually performed by complementary addition (1s complement), a carry out means borrow; thus, a carry is generated when there is no under-flow and no carry is generated when there is underflow. As indicated, the "181" can be used with either active LOW inputs producing active LOW outputs or with active HIGH inputs producing active HIGH outputs. For either case the table lists the operations that are performed to the operands.
VERSION SOT222-1 SOT101-1 SOT137-1
1998 Jun 10
2
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
74HC/HCT181
TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay An or Bn to A=B Cn to Cn+4 CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V input capacitance power dissipation capacitance per L package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 28 17 3.5 90 30 21 3.5 92 ns ns pF pF HCT UNIT
A
B
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
1998 Jun 10
3
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
PIN DESCRIPTION PIN NO. 1, 22, 20, 18 2, 23, 21, 19 6, 5, 4, 3 7 8 9, 10, 11, 13 12 14 15 16 17 24 SYMBOL B0 to B3 A0 to A3 S0 to S3 Cn M F0 to F3 GND A=B P Cn+4 G VCC NAME AND FUNCTION operand inputs (active LOW) operand inputs (active LOW) select inputs carry input mode control input function outputs (active LOW) ground (0 V) comparator output carry propagate output (active LOW) carry output carry generate output (active LOW) positive supply voltage
74HC/HCT181
ok, halfpage
2 23 21 19 1 22 20 18 7 6 5 4 3 8
A0 A1 A2 A3 B0 B1 B2 B3 Cn S0 S1 S2 S3 M
F0 9 F1 10 F2 11 F3 13 Cn+4 16 A=B G P 14 17 15
MBK219
Fig.4 Functional diagram.
Fig.5 Active HIGH operands - active LOW operands.
1998 Jun 10
4
Philips Semiconductors
Product specification
4-bit arithmetic logic unit
FUNCTION TABLES MODE SELECT INPUTS S3 L L L L L L L L H H H H H H H H S2 L L L L H H H H L L L L H H H H S1 L L H H L L H H L L H H L L H H S0 L H L H L H L H L H L H L H L H ACTIVE HIGH INPUTS AND OUTPUTS LOGIC (M=H) A A+B AB logical 0 AB B AB AB A+B AB B AB logical 1 A+B A+B A ARITHMETIC(2) (M=L; Cn=H) A A+B A+B minus 1 A plus AB (A + B) plus AB A minus B minus 1 AB minus 1 A plus AB A plus B (A + B) plus AB AB minus 1 A plus A(1) (A + B) plus A (A + B) plus A A minus 1 MODE SELECT INPUTS S3 L L L L L L L L H H H H H H H H S2 L L L L H H H H L L L L H H H H S1 L L H H L L H H L L H H L L H H S0 L H L H L H L H L H L H L H L H
74HC/HCT181
ACTIVE LOW INPUTS AND OUTPUTS LOGIC (M=H) A AB A+B logical 1 A+B B AB A+B AB AB B A+B logical 0 AB AB A ARITHMETIC(2) (M=L; Cn=L) A minus 1 AB minus 1 AB minus 1 minus 1 A plus (A + B) AB plus (A + B) A minus B minus 1 A+B A plus (A + B) A plus B AB plus (A + B) A+B A plus A(1) AB plus A AB plus A A
Notes to the function tables 1. Each bit is shifted to the next more significant position. 2. Arithmetic operations expressed in 2s complement notation. H = HIGH voltage level L = LOW voltage level
Notes to the function tables 1. Each bit is shifted to the next more significant position. 2. Arithmetic operations expressed in 2s complement notation. H = HIGH voltage level L = LOW voltage level
1998 Jun 10
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