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Part: 74HC/HCT191
Category:
Logic
-> Counters
-> Synchronous Counters-> CMOS/BiCMOS->HC/HCT Family
Description: Presettable Synchronous 4-bit Binary Up/down Counter
Company: Philips Semiconductors
Datasheet: Download 74HC/HCT191 datasheet File size : 156 kB
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
· The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications · The IC06 74HC/HCT/HCU/HCMOS Logic Package Information · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT191 Presettable synchronous 4-bit binary up/down counter
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary up/down counter
FEATURES · Synchronous reversible counting · Asynchronous parallel load · Count enable control for synchronous expansion · Single up/down control input · Output capability: standard · ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT191 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT191 are asynchronously presettable 4-bit binary up/down counters. They contain four master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operation. Asynchronous parallel load capability permits the counter to be preset to any desired number. Information present on the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs when the parallel load (PL) input is LOW. As indicated in the function table, this operation overrides the counting function. Counting is inhibited by a HIGH level on the count enable (CE) input. When CE is LOW internal state changes are initiated synchronously by the LOW-to-HIGH transition of the clock input. The up/down (U/D) input signal determines the direction of counting as indicated in the function table. The CE input may go LOW when the clock is in either state, however, the LOW-to-HIGH CE transition must occur only when the clock is HIGH. Also, the U/D input should be changed only when either CE or CP is HIGH.
74HC/HCT191
Overflow/underflow indications are provided by two types of outputs, the terminal count (TC) and ripple clock (RC). The TC output is normally LOW and goes HIGH when a circuit reaches zero in the count-down mode or reaches "15" in the count-up-mode. The TC output will remain HIGH until a state change occurs, either by counting or presetting, or until U/D is changed. Do not use the TC output as a clock signal because it is subject to decoding spikes. The TC signal is used internally to enable the RC output. When TC is HIGH and CE is LOW, the RC output follows the clock pulse (CP). This feature simplifies the design of multistage counters as shown in Figs 5 and 6. In Fig.5, each RC output is used as the clock input to the next higher stage. It is only necessary to inhibit the first stage to prevent counting in all stages, since a HIGH on CE inhibits the RC output pulse as indicated in the function table. The timing skew between state changes in the first and last stages is represented by the cumulative delay of the clock as it ripples through the preceding stages. This can be a disadvantage of this configuration in some applications. Fig.6 shows a method of causing state changes to occur simultaneously in all stages. The RC outputs propagate the carry/borrow signals in ripple fashion and all clock inputs are driven in parallel. In this configuration the duration of the clock LOW state must be long enough to allow the negative-going edge of the carry/borrow signal to ripple through to the last stage before the clock goes HIGH. Since the RC output of any package goes HIGH shortly after its CP input goes HIGH there is no such restriction on the HIGH-state duration of the clock. In Fig.7, the configuration shown avoids ripple delays and their associated restrictions. Combining the TC signals from all the preceding stages forms the CE input for a given stage. An enable must be included in each carry gate in order to inhibit counting. The TC output of a given stage it not affected by its own CE signal therefore the simple inhibit scheme of Figs 5 and 6 does not apply.
December 1990
2
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary up/down counter
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
74HC/HCT191
TYPICAL SYMBOL tPHL/ tPLH fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC -1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay CP to Qn maximum clock frequency input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 22 36 3.5 31 HCT 22 36 3.5 33 ns MHz pF pF UNIT
December 1990
3
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary up/down counter
PIN DESCRIPTION PIN NO. 3, 2, 6, 7 4 5 8 11 12 13 14 15, 1, 10, 9 16 SYMBOL Q0 to Q3 CE U/D GND PL TC RC CP D0 to D3 VCC NAME AND FUNCTION flip-flop outputs count enable input (active LOW) up/down input ground (0 V) parallel load input (active LOW) terminal count output ripple clock output (active LOW)
74HC/HCT191
clock input (LOW-to-HIGH, edge triggered) data inputs positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
4
Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary up/down counter
74HC/HCT191
Fig.4 Functional diagram.
FUNCTION TABLE INPUTS OPERATING MODE PL parallel load count up count down hold (do nothing) TC AND RC FUNCTION TABLE INPUTS U/D H L L L H H Notes 1. H = HIGH voltage level L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition X = don't care = LOW-to-HIGH CP transition = one LOW level pulse = TC goes LOW on a LOW-to-HIGH CP transition CE H H L H H L CP X X X X Q0 H H H L L L TERMINAL COUNT STATE Q1 H H H L L L Q2 H H H L L L Q3 H H H L L L OUTPUTS TC L H L H RC H H H H L L H H H U/D X X L H X CE X X I I H CP X X X Dn L H X X X Qn L H count up count down no change OUTPUTS
December 1990
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