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Details, datasheet, quote on part number:74HC/HCT192
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| Part: | 74HC/HCT192 |
| Category: | Logic => Counters => Synchronous Counters-> CMOS/BiCMOS->HC/HCT Family |
| Description: | Presettable Synchronous BCD Decade Up/down Counter |
| Company: | Philips Semiconductors |
| Datasheet: | Download 74HC/HCT192 datasheet File size : 92 kB |
| Request For quote: | Find where to buy 74HC/HCT192
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Datasheet text preview:
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
· The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications · The IC06 74HC/HCT/HCU/HCMOS Logic Package Information · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT192 Presettable synchronous BCD decade up/down counter
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
Presettable synchronous BCD decade up/down counter
FEATURES · Synchronous reversible counting · Asynchronous parallel load · Asynchronous reset · Expandable without external logic · Output capability: standard · ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT192 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT192 are synchronous BCD up/down counters. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at any time, or erroneous operation will result. The device can be cleared at any time by the asynchronous master reset input (MR); it may also be loaded in parallel by activating the asynchronous parallel load input (PL). The "192" contains four master-slave JK flip-flops with the necessary steering logic to provide the asynchronous reset, load, and synchronous count up and count down functions. Each flip-flop contains JK feedback from slave to master, such that a LOW-to-HIGH transition on the CPD input will decrease the count by one, while a similar transition on the CPU input will advance the count by one.
74HC/HCT192
One clock should be held HIGH while counting with the other, otherwise the circuit will either count by two's or not at all, depending on the state of the first flip-flop, which cannot toggle as long as either clock input is LOW. Applications requiring reversible operation must make the reversing decision while the activating clock is HIGH to avoid erroneous counts. The terminal count up (TCU) and terminal count down (TCD) outputs are normally HIGH. When the circuit has reached the maximum count state of 9, the next HIGH-to-LOW transition of CPU will cause TCU to go LOW. TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise, the TCD output will go LOW when the circuit is in the zero state and the CPD goes LOW. The terminal count outputs can be used as the clock input signals to the next higher order circuit in a multistage counter, since they duplicate the clock waveforms. Multistage counters will not be fully synchronous, since there is a slight delay time difference added for each stage that is added. The counter may be preset by the asynchronous parallel load capability of the circuit. Information present on the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs (Q0 to Q3) regardless of the conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on the master reset (MR) input will disable the parallel load gates, override both clock inputs and set all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted as a legitimate signal and will be counted.
December 1990
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Philips Semiconductors
Product specification
Presettable synchronous BCD decade up/down counter
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
74HC/HCT192
TYPICAL SYMBOL tPHL/ tPLH fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC -1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay CPD, CPU to Qn maximum clock frequency input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 20 40 3.5 24 HCT 20 45 3.5 28 ns MHz pF pF UNIT
December 1990
3
Philips Semiconductors
Product specification
Presettable synchronous BCD decade up/down counter
PIN DESCRIPTION PIN NO. 3, 2, 6, 7 4 5 8 11 12 13 14 15, 1, 10, 9 16 Note 1. LOW-to-HIGH, edge triggered SYMBOL Q0 to Q3 CPD CPU GND PL TCU TCD MR D0 to D3 VCC NAME AND FUNCTION flip-flop outputs count down clock input(1) count up clock input(1) ground (0 V)
74HC/HCT192
asynchronous parallel load input (active LOW) terminal count up (carry) output (active LOW) terminal count down (borrow) output (active LOW) asynchronous master reset input (active HIGH) data inputs positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
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Philips Semiconductors
Product specification
Presettable synchronous BCD decade up/down counter
FUNCTION TABLE INPUTS OPERATING MODE MR reset (clear) H H L parallel load L L L count up count down Notes 1. H = HIGH voltage level L = LOW voltage level X = don't care = LOW-to-HIGH clock transition 2. TCU = CPU at terminal count up (HLLH) 3. TCD = CPD at terminal count down (LLLL) L L PL X X L L L L H H CPU CPD X X X X L H H L H L H X X H D0 X X L L H H X X D1 X X L L X X X X D2 X X L L X X X X D3 X X L L H H X X Q0 L L L L Q1 L L L L
74HC/HCT192
OUTPUTS Q2 L L L L Q n = Dn Q n = Dn count up count down Q3 L L L L TCU H H H H L H H(2) H TCD L H L H H H H H(3)
Fig.4 Functional diagram.
December 1990
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