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Details, datasheet, quote on part number:74HC/HCT194
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INTEGRATED CIRCUITS
DATA SHEET
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· The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications · The IC06 74HC/HCT/HCU/HCMOS Logic Package Information · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT194 4-bit bidirectional universal shift register
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
FEATURES · Shift-left and shift-right capability · Synchronous parallel and serial data transfer · Easily expanded for both serial and parallel operation · Asynchronous master reset · Hold ("do nothing") mode · Output capability: standard · ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT194 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The functional characteristics of the 74HC/HCT194 4-bit bidirectional universal shift registers are indicated in the logic diagram and function table. The registers are fully synchronous. The "194" design has special features which increase the range of application. The synchronous operation of the device is determined by the mode select inputs (S0, S1). As shown in the mode select table, data can be entered QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
74HC/HCT194
and shifted from left to right (Q0 Q1 Q2, etc.) or, right to left (Q3 Q2 Q1, etc.) or parallel data can be entered, loading all 4 bits of the register simultaneously. When both S0 and S1 are LOW, existing data is retained in a hold ("do nothing") mode. The first and last stages provide D-type serial data inputs (DSR, DSL) to allow multistage shift right or shift left data transfers without interfering with parallel load operation. Mode select and data inputs are edge-triggered, responding only to the LOW-to-HIGH transition of the clock (CP). Therefore, the only timing restriction is that the mode control and selected data inputs must be stable one set-up time prior to the positive transition of the clock pulse. The four parallel data inputs (D0 to D3) are D-type inputs. Data appearing on the D0 to D3 inputs, when S0 and S1 are HIGH, is transferred to the Q0 to Q3 outputs respectively, following the next LOW-to-HIGH transition of the clock. When LOW, the asynchronous master reset (MR) overrides all other input conditions and forces the Q outputs LOW. The "194" is similar in operation to the "195" universal shift register, with added features of shift-left without external connections and hold ("do nothing") modes of operation.
TYPICAL SYMBOL tPHL/ tPLH tPHL fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz = (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC - 1.5 V December 1990 2 PARAMETER propagation delay CP to Qn MR to Qn maximum clock frequency input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 14 11 102 3.5 40 15 15 77 3.5 40 ns ns MHz pF pF HCT UNIT
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PIN DESCRIPTION PIN NO. 1 2 3, 4, 5, 6 7 8 9, 10 11 15, 14, 13, 12 16 SYMBOL MR DSR D0 to D3 DSL GND S0, S1 CP Q0 to Q3 VCC NAME AND FUNCTION asynchronous master reset input (active LOW) serial data input (shift right) parallel data inputs serial data input (shift left) ground (0 V) mode control inputs clock input (LOW-to-HIGH edge-triggered) parallel outputs positive supply voltage
74HC/HCT194
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
74HC/HCT194
Fig.4 Functional diagram.
FUNCTION TABLE INPUTS OPERATING MODES CP reset (clear) hold ("do nothing") shift left shift right parallel load Notes 1. H h L I q,d X = HIGH voltage level = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition = LOW voltage level = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition = lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW-to-HIGH CP transition = don't care = LOW-to-HIGH CP transition X X MR L H H H H H H S1 X I h h I I h S0 X I I I h h h DSR X X X X I h X DSL X X I h X X X Dn X X X X X X dn Q0 L q0 q1 q1 L H d0 Q1 L q1 q2 q2 q0 q0 d1 Q2 L q2 q3 q3 q1 q1 d2 Q3 L q3 L H q2 q2 d3 OUTPUTS
December 1990
4
Philips Semiconductors
Product specification
4-bit bidirectional universal shift register
74HC/HCT194
Fig.5 Logic diagram.
Fig.6 Typical clear, clear-load, shift-right, shift-left, inhibit and clear timing sequences.
December 1990
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