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Details, datasheet, quote on part number:74HC/HCT7404
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Datasheet text preview:
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
· The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications · The IC06 74HC/HCT/HCU/HCMOS Logic Package Information · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7404 5-Bit x 64-word FIFO register; 3-state
Product specification Supersedes data of October 1990 File under Integrated Circuits, IC06 September 1993
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
FEATURES · Synchronous or asynchronous operation · 3-state outputs · 30 MHz (typical) shift-in and shift-out rates · Readily expandable in word and bit dimensions · Pinning arranged for easy board layout: input pins directly opposite output pins · Output capability: driver (8 mA) · ICC category: LSI. APPLICATIONS · High-speed disc or tape controller · Communications buffer. GENERAL DESCRIPTION
74HC/HCT7404
The 74HC/HCT7404 are high-speed Si-gate CMOS devices specified in compliance with JEDEC standard no.7A. The "7404" is an expandable, First-In First-Out (FIFO) memory organized as 64 words by 5 bits. A guaranteed 15 MHz data-rate makes it ideal for high-speed applications. A higher data-rate can be obtained in applications where the status flags are not used (burst-mode). With separate controls for shift-in (SI) and shift-out (SO), reading and writing operations are completely independent, allowing synchronous and asynchronous data transfers. Additional controls include a master-reset input (MR), an output enable input (OE) and flags. The data-in-ready (DIR) and data-out-ready (DOR) flags indicate the status of the device.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. TYP. SYMBOL tPHL/tPLH fmax CI CPD Note 1. For HC the condition is VI = GND to VCC. For HCT the condition is VI = GND to VCC -1.5 V. ORDERING INFORMATION EXTENDED TYPE NUMBER 74HC/HCT7404N 74HC/HCT7404D PACKAGE PINS 18 20 PIN POSITION DIL SO20 MATERIAL plastic plastic CODE SOT102 SOT163A PARAMETER propagation delay SO, SI to DIR and DOR maximum clock frequency input capacitance power dissipation capacitance per package note 1 CONDITIONS HC CL = 15 pF; VCC = 5 V 15 30 3.5 475 HCT 17 30 3.5 490 ns MHz pF pF UNIT
September 1993
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Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
PINNING (SOT102) SYMBOL OE DIR SI DO to D4 GND MR Q4 to Q0 DOR SO VCC PIN 1 2 3 9 10 11, 12, 13, 14, 15 16 17 18 DESCRIPTION output enable input (active LOW) data-in-ready output shift-in input (active HIGH) ground asynchronous master-reset input (active LOW) data outputs Q4 to Q0 data-out-ready output shift-out input (active LOW) positive supply voltage n.c. DOR n.c. VCC 12, 13, 14, 15, 16 17 18 19 20 PINNING (SOT163A) SYMBOL OE DIR SI n.c. D0 to D4 GND MR PIN 1 2 3 4 10 11
74HC/HCT7404
DESCRIPTION output enable input (active LOW) data-in-ready output shift-in input (active HIGH) not connected ground asynchronous master-reset input (active LOW) data outputs not connected data-out ready output not connected positive supply voltage
4, 5, 6, 7, 8 parallel data inputs
5, 6, 7, 8, 9 parallel data inputs
handbook, halfpage handbook, halfpage
OE OE DIR SI D0 D1 D2 D3 D4 GND 1 2 3 4 5 6 7 8 9
MGA670
1 2 3 4 5
18 V C C 17 SO
20 V C C 19 SO 18 DOR 17 n.c. 16 Q0
DIR SI
16 DOR n.c. 15 Q0 D0 D1 D2 D3 D4
7404
14 Q1 13 Q2 12 Q3 11 Q4 10 MR
7404
6 7 8 9 15 Q1 14 Q2 13 Q3 12 Q4 11 MR
MGA671
GND 10
Fig.1 Pin configuration (SOT102).
Fig.2 Pin configuration (SOT163).
September 1993
3
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
handbook, halfpage
1 (1)
handbook, halfpage
FIFO 64 x 5 EN4 1Z3 [IR] 3 [OR] 6 G1 G5 2 (2) 16 (18)
(1) 1 OE (5) 4 (6) 5 (7) 6 (8) 7 (9) 8 D0 D1 D2 D3 D4 SI SO MR 10 (11)
MGA673
Q0 Q1 Q2 Q3 Q4 DOR DIR
15 (16) 14 (15) 13 (14) 12 (13) 11 (12) (5) 4 (6) 5 (7) 6 (8) 7 (9) 8 (3) 3 (11) 10 (19) 17
CTR 1 ( /C2) CT 0 5 5Z6 2D
(3) 3 (19) 17
16 (18) 2 (2)
4
15 (16) 14 (15) 13 (14) 12 (13) 11 (12)
MGA675
Pin numbers between parentheses refer to the SO package.
Pin numbers between parentheses refer to the SO package.
Fig.3 Logic symbol.
Fig.4 IEC logic symbol.
handbook, full pagewidth
(5) 4 D0 (6) 5 D1 (7) 6 D2 (8) 7 D3 (9) 8 D4 INPUT STAGE 1 x 5 BITS MAIN FIFO REGISTER 62 x 5 BITS OUTPUT STAGE 1 x 5 BITS
Q 0 15 (16) Q 1 14 (15) Q 2 13 (14) Q 3 12 (13) OE Q 4 11 (12)
(11) 10 MR DIR 2 (2) SI
CONTROL LOGIC DOR SO OE 1 (1)
MGA680
3 (3)
16 (18) 17 (19)
Pin numbers between parentheses refer to the SO package.
Fig.5 Functional diagram.
September 1993
4
full pagewidth
R (1) R S Q FP DOR
September 1993
SO
Philips Semiconductors
MR
61 x
SI
(1) R R FF1 S Q S Q S R FF2 R FF64 Q Q R Q R R Q
(2)
(2)
(2)
(1)
R
FS
5-Bit x 64-word FIFO register; 3-state
S
Q
Q FF3 R to FF63 S Q
R S
FB Q
5
OE CL CL CL CL CL CL CL Q0 Q1 5 LATCHES 5 LATCHES 5 LATCHES 3-STATE OUTPUT BUFFER Q3 Q4 position 2 position 3 to 63 position 64
MSB117
DIR
D0
CL
D1
5 LATCHES
D3
D4
position 1
(See control flip-flops)
LOW on S input of flip-flops FS, FB and FP will set Q output to HIGH independent of state on R input.
LOW on R input of FF1 to FF64 will set Q output to LOW independent of state on S input.
74HC/HCT7404
Product specification
Fig.6 Logic diagram.
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