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Details, datasheet, quote on part number: 74HC/HCT93
 
 
Part number74HC/HCT93
CategoryLogic => Counters => CMOS/BiCMOS->HC/HCT Family
TitleCMOS/BiCMOS->HC/HCT Family
Description4-bit Binary Ripple Counter
CompanyPhilips Semiconductors (Acquired by NXP)
DatasheetDownload 74HC/HCT93 datasheet
 


 
Specifications, Features, Applications

For a complete data sheet, please also download:

· The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications· The IC06 74HC/HCT/HCU/HCMOS Logic Package Information· The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

Product specification File under Integrated Circuits, IC06 December 1990

FEATURES· Various counting modes· Asynchronous master reset· Output capability: standard· ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT93 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT93 are 4-bit binary ripple counters. The devices consist of four master-slave flip-flops internally connected to provide a QUICK REFERENCE DATA GND 0 V; Tamb = 25 °C; 6 ns divide-by-two section and a divide-by-eight section. Each section has a separate clock input (CP0 and CP1) to initiate state changes of the counter on the HIGH-to-LOW clock transition. State changes of the Qn outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes. A gated AND asynchronous master reset (MR1 and MR2) is provided which overrides both clocks and resets (clears) all flip-flops. Since the output from the divide-by-two section is not internally connected to the succeeding stages,

the device may be operated in various counting modes. a 4-bit ripple counter the output Q0 must be connected externally to input CP1. The input count pulses are applied to clock input CP0. Simultaneous frequency divisions 4, 8 and 16 are performed at the Q1, Q2 and Q3 outputs as shown in the function table. a 3-bit ripple counter the input count pulses are applied to input CP1. Simultaneous frequency divisions 2, 4 and 8 are available at the Q1, Q2 and Q3 outputs. Independent use of the first flip-flop is available if the reset function coincides with reset of the 3-bit ripple-through counter.

TYPICAL SYMBOL tPHL/ tPLH fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD fi + (CL VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz (CL VCC2 × fo) = sum of outputs CL = output load capacitance in pF; VCC = supply voltage V 2. For HC the condition VI = GND to VCC; for HCT the condition VI = GND to VCC 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay to Q0 maximum clock frequency input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS = 15 pF; VCC 5 V HCT ns MHz pF UNIT

clock input 2nd, 3rd and 4th section (HIGH-to-LOW, edge-triggered) asynchronous master reset (active HIGH) not connected positive supply voltage ground (0 V) flip-flop outputs clock input 1st section (HIGH-to-LOW, edge-triggered)




Some Part number from the same manufacture Philips Semiconductors (Acquired by NXP)
74HC00 74HC00; 74HCT00; Quad 2-input NAND Gate;; Package: SOT108-1 (SO14), SOT27-1 (DIP14), SOT337-1 (SSOP14), SOT402-1 (TSSOP14), Uncased Die
74HC02 74HC/HCT02; Quad 2-input NOR GATE;; Package: SOT108-1 (SO14), SOT27-1 (DIP14), SOT337-1 (SSOP14), SOT402-1 (TSSOP14)
74HC03 74HC/HCT03; Quad 2-input NAND Gate;; Package: SOT108-1 (SO14), SOT27-1 (DIP14), SOT337-1 (SSOP14), SOT402-1 (TSSOP14)
74HC04 74HC04; 74HCT04; Hex Inverter;; Package: SOT108-1 (SO14), SOT27-1 (DIP14), SOT337-1 (SSOP14), SOT402-1 (TSSOP14)
74HC08 74HC08; 74HCT08; Quad 2-input And Gate;; Package: SOT108-1 (SO14), SOT27-1 (DIP14), SOT337-1 (SSOP14), SOT402-1 (TSSOP14)
74HC10 74HC/HCT10; Triple 3-input NAND Gate;; Package: SOT108-1 (SO14), SOT27-1 (DIP14), SOT337-1 (SSOP14), SOT402-1 (TSSOP14)
74HC107 74HC/HCT107; Dual JK Flip-flop With Reset; Negative-edge Trigger
74HC107D 74HC/HCT107; Dual JK Flip-flop With Reset; Negative-edge Trigger;; Package: SOT108-1 (SO14)
74HC107U 74HC/HCT107; Dual JK Flip-flop With Reset; Negative-edge Trigger
74HC109 74HC/HCT109; Dual JK Flip-flop With Set And Reset; Positive-edge Trigger
74HC109D 74HC/HCT109; Dual JK Flip-flop With Set And Reset; Positive-edge Trigger;; Package: SOT109-1 (SO16)
74HC109U 74HC/HCT109; Dual JK Flip-flop With Set And Reset; Positive-edge Trigger
74HC10D 74HC/HCT10; Triple 3-input NAND Gate;; Package: SOT108-1 (SO14), SOT27-1 (DIP14), SOT337-1 (SSOP14), SOT402-1 (TSSOP14)
74HC11 74HC/HCT11; Triple 3-input And Gate;; Package: SOT108-1 (SO14), SOT27-1 (DIP14), SOT337-1 (SSOP14), SOT402-1 (TSSOP14)
74HC112 74HC112;74HCT112; Dual JK Flip-flop With Set And Reset; Negative-edge Trigger
74HC112D 74HC112;74HCT112; Dual JK Flip-flop With Set And Reset; Negative-edge Trigger;; Package: SOT109-1 (SO16)
74HC112U 74HC112;74HCT112; Dual JK Flip-flop With Set And Reset; Negative-edge Trigger
74HC11D 74HC/HCT11; Triple 3-input And Gate;; Package: SOT108-1 (SO14), SOT27-1 (DIP14), SOT337-1 (SSOP14), SOT402-1 (TSSOP14)
74HC123 74HC/HCT123; Dual Retriggerable Monostable Multivibrator With Reset;; Package: SOT109-1 (SO16), SOT338-1 (SSOP16), SOT38-4 (DIP16), SOT403-1 (TSSOP16)
74HC125 74HC/HCT125; Quad Buffer/line Driver; 3-state;; Package: SOT108-1 (SO14), SOT27-1 (DIP14), SOT337-1 (SSOP14), SOT402-1 (TSSOP14)
74HC126 74HC/HCT126; Quad Buffer/line Driver; 3-state;; Package: SOT108-1 (SO14), SOT27-1 (DIP14), SOT337-1 (SSOP14), SOT402-1 (TSSOP14)