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Details, datasheet, quote on part number:74LV377PWDH
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| Part: | 74LV377PWDH |
| Category: | Logic => Flip-Flops |
| Description: | 74LV377; Octal D-type Flip-flop With Data Enable; Positive Edge-trigger;; Package: SOT360-1 (TSSOP20) |
| Company: | Philips Semiconductors |
| Datasheet: | Download 74LV377PWDH datasheet File size : 127 kB |
| Request For quote: | Find where to buy 74LV377PWDH
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Datasheet text preview:
INTEGRATED CIRCUITS
74LV377 Octal D-type flip-flop with data enable; positive edge-trigger
Product specification Supersedes data of 1997 Mar 04 IC24 Data Handbook 1998 Jun 10
Philips Semiconductors
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable; positive edge-trigger
74LV377
FEATURES
· Optimized for Low Voltage applications: 1.0 to 3.6V · Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V · Typical VOLP (output ground bounce) t 0.8V @ VCC = 3.3V, · Typical VOHV (output VOH undershoot) u 2V @ VCC = 3.3V, · Ideal for addressable register applications · Data enable for address and data synchronization applications · Eight positive-edge triggered D-type flip-flops · Output capability: standard · ICC category: MSI
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf v2.5 ns SYMBOL tPHL/tPLH fmax CI CP D PARAMETER Propagation delay CP to Qn Maximum clock frequency Input capacitance Power dissipation capacitance per flip-flop Tamb = 25°C Tamb = 25°C
DESCRIPTION
The 74LV377 is a lowvoltage CMOS device and is pin and function compatible with 74HC/HCT377. The 74LV377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A common clock (CP) input loads all flip-flops simultaneously when the data enable (E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. The E input must be stable only one set-up time prior to the LOW-to-HIGH transition for predictable operation.
CONDITIONS CL = 15pF VCC = 3.3V 3 3V
TYPICAL 13 77 3.5 20
UNIT ns MHz pF pF
Notes 1 and 2
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) VCC2 fi )S (CL VCC2 fo) where: PD = CPD fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; VCC2 fo) = sum of the outputs. S (CL 2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES 20-Pin Plastic DIL 20-Pin Plastic SO 20-Pin Plastic SSOP Type II 20-Pin Plastic TSSOP Type I TEMPERATURE RANGE 40°C to +125°C 40°C to +125°C 40°C to +125°C 40°C to +125°C OUTSIDE NORTH AMERICA 74LV377 N 74LV377 D 74LV377 DB 74LV377 PW NORTH AMERICA 74LV377 N 74LV377 D 74LV377 DB 74LV377PW DH PKG. DWG. # SOT146-1 SOT163-1 SOT339-1 SOT360-1
PIN DESCRIPTION
PIN NUMBER 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 10 11 20 SYMBOL E Q0 to Q7 D0 to D7 GND CP VCC FUNCTION Data enable input (active-LOW) flip-flop outputs Data inputs Ground (0V) Clock input (LOW-to-HIGH, edge-triggered) Positive supply voltage
FUNCTION TABLE
OPERATING MODES MODES Load ``1'' Load ``0'' Hold (do nothing) H h L l X INPUTS CP X E l l h H Dn h l X X OUTPUTS Qn H L No change No change
= HIGH voltage level = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition = LOW voltage level = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition = LOWtoHIGH CP transition = Don't care
1998 Jun 10
2
8531935 19545
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable; positive edge-trigger
74LV377
PIN CONFIGURATION
LOGIC SYMBOL (IEEE/IEC)
11 E Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP 3 1
1C2 G1
2D
2
4 7 8 13 14 17 18
5 6 9 12 15 16 19
SV00667
SV00669
LOGIC SYMBOL
FUNCTIONAL DIAGRAM
11 3 3 4 7 8 13 14 17 18 D0 D1 D2 D3 D4 D5 D6 D7 E CP Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 1 11 1 E CP 4 7 8 13 14 17 18 D0 D1 D2 D3 D4 D5 D6 D7 FF1 to FF8 OUTPUTS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19
SV00668
SV00670
1998 Jun 10
3
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable; positive edge-trigger
74LV377
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VI VO Tamb DC supply voltage Input voltage Output voltage Operating ambient temperature range in free air See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V PARAMETER CONDITIONS See Note 1 MIN 1.0 0 0 40 40 TYP 3.3 MAX 3.6 VCC VCC +85 +125 500 200 100 UNIT V V V °C
tr, tf
Input rise and fall times
ns/V
NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 3.6V.
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V). SYMBOL VCC ħIIK ħIOK ħIO ħIGND, ħICC Tstg PARAMETER DC supply voltage DC input diode current DC output diode current DC output source or sink current standard outputs DC VCC or GND current for types with standard outputs Storage temperature range Power dissipation per package plastic DIL plastic mini-pack (SO) plastic shrink mini-pack (SSOP and TSSOP) for temperature range: 40 to +125°C above +70°C derate linearly with 12mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K VI VCC + 0.5V VO VCC + 0.5V 0.5V < VO < VCC + 0.5V CONDITIONS RATING 0.5 to +4.6 20 50 25 UNIT V mA mA mA
50 65 to +150 750 500 400
mA °C
Ptot
mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Jun 10
4
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable; positive edge-trigger
74LV377
DC CHARACTERISTICS FOR THE LV FAMILY
Over recommended operating conditions. Voltages are referenced to GND (ground = 0V). LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN VCC = 1.2V VIH HIGH l level I l Input t voltage VCC = 2.0V VCC = 2.7 to 3.6V VCC = 1.2V VIL LOW l level I l Input t voltage VCC = 2.0V VCC = 2.7 to 3.6V VCC = 1.2V; VI = VIH or VIL; IO = 100µA HIGH level output voltage; all outputs VOH HIGH level output voltage; STANDARD outputs VCC = 2.0V; VI = VIH or VIL; IO = 100µA VCC = 2.7V; VI = VIH or VIL; IO = 100µA VCC = 3.0V; VI = VIH or VIL; IO = 100µA VCC = 3.0V; VI = VIH or VIL; IO = 6mA VCC = 1.2V; VI = VIH or VIL; IO = 100µA LOW level output voltage; all outputs VOL LOW level output voltage; STANDARD outputs II ICC ICC Input leakage current Quiescent supply current; MSI Additional quiescent supply current per input VCC = 2.0V; VI = VIH or VIL; IO = 100µA VCC = 2.7V; VI = VIH or VIL; IO = 100µA VCC = 3.0V; VI = VIH or VIL; IO = 100µA VCC = 3.0V; VI = VIH or VIL; IO = 6mA 1.8 2.5 2.8 2.40 1.2 2.0 2.7 3.0 2.82 0 0 0 0 0.25 0.2 0.2 0.2 0.40 0.2 0.2 0.2 0.50 V 1.8 2.5 2.8 2.20 V 0.9 1.4 2.0 0.3 0.6 0.8 -40°C to +85°C TYP1 MAX -40°C to +125°C MIN 0.9 1.4 2.0 0.3 0.6 0.8 V V MAX UNIT
VCC = 3.6V; VI = VCC or GND VCC = 3.6V; VI = VCC or GND; IO = 0 VCC = 2.7V to 3.6V; VI = VCC 0.6V
1.0 20.0 500
1.0 160 850
µA µA µA
NOTE: 1. All typical values are measured at Tamb = 25°C.
1998 Jun 10
5
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