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Details, datasheet, quote on part number:74LVC139
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| Part: | 74LVC139 |
| Category: | Logic => Decoders/Demultiplexers |
| Description: | 74LVC139; Dual 2-to-4 Line Decoder/demultiplexer;; Package: SOT109-1 (SO16), SOT338-1 (SSOP16), SOT403-1 (TSSOP16), SOT763-1 (DHVQFN16) |
| Company: | Philips Semiconductors |
| Datasheet: | Download 74LVC139 datasheet File size : 105 kB |
| Request For quote: | Find where to buy 74LVC139
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Datasheet text preview:
INTEGRATED CIRCUITS
DATA SHEET
74LVC139 Dual 2-to-4 line decoder/demultiplexer
Product specification Supersedes data of 1998 Apr 28 2003 May 19
Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
FEATURES · Wide supply voltage range from 1.2 to 3.6 V · Inputs accept voltages up to 5.5 V · CMOS low power consumption · Direct interface with TTL levels · Demultiplexing capability · Two independent 2-to-4 decoders · Multifunction capability · Active LOW mutually exclusive outputs · Output drive capability 50 transmission lines at 85 °C · In accordance with JEDEC standard no. 8-1A · ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf 2.5 ns. SYMBOL tPHL/tPLH nA to nYn nE to nYn CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; (CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. input capacitance PARAMETER propagation delay CONDITIONS CL = 50 pF; VCC = 3.3 V 3.3 3.2 5.0 DESCRIPTION
74LVC139
The 74LVC139 is a high-performance, low-voltage and low-power Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC139 is a dual 2-to-4 line decoder/demultiplexer. This device has two independent decoders, each accepting two binary weighted inputs (nA0 and nA1) and providing four mutually exclusive active LOW outputs (nY0 to nY3). Each decoder has an active LOW input (nE). When nE is HIGH, every output is forced HIGH. The enable input can be used as the data input for a 1-to-4 demultiplexer application.
TYPICAL ns ns pF pF
UNIT
power dissipation capacitance per multiplexer VCC = 3.3 V; notes 1 and 2 36
2003 May 19
2
Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
FUNCTION TABLE See note 1 INPUT nE H L L L L Note 1. H = HIGH voltage level; L = LOW voltage level; X = don't care. ORDERING INFORMATION PACKAGE TYPE NUMBER 74LVC139D 74LVC139DB 74LVC139PW 74LVC139BQ TEMPERATURE RANGE -40 to +85 °C -40 to +85 °C -40 to +85 °C -40 to +85 °C PINS 16 16 16 16 PACKAGE SO16 SSOP16 TSSOP16 DHVQFN16 MATERIAL plastic plastic plastic plastic nA0 X L H L H nA1 X L L H H nY0 H L H H H nY1 H H L H H OUTPUT nY2 H H H L H
74LVC139
nY3 H H H H L
CODE SOT109-1 SOT338-1 SOT403-1 SOT763-1
2003 May 19
3
Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
PINNING PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1E 1A0 1A1 1 Y0 1 Y1 1 Y2 1 Y3 GND 2 Y3 2Y2 2Y1 2Y0 2A1 2A0 2E VCC SYMBOL enable input (active LOW) address input address input output (active LOW) output (active LOW) output (active LOW) output (active LOW) ground (0 V) output (active LOW) output (active LOW) output (active LOW) output (active LOW) address input address input enable input (active LOW) positive supply voltage DESCRIPTION
74LVC139
handbook, halfpage
1E 1
VCC 16 15 14 13 2E 2A0 2A1 2Y0 2Y1 2Y2
handbook, halfpage
1E 1 1A0 2 1A1 3 1Y0 4 1Y1 5 1Y2 6 1Y3 7 GND 8
MNA778
16 VCC 15 2E 14 2A0
1A0 1A1 1Y0 1Y1 1Y2 1Y3
2 3 4
139
13 2A1
5 6 7
GND(1)
12 11 10 8 Top view GND 9 2Y3
MNA972
12 2Y0 11 2Y1 10 2Y2 9 2Y3
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
Fig.1 Pin configuration SO16 and (T)SSOP16.
Fig.2 Pin configuration DHVQFN16.
2003 May 19
4
Philips Semiconductors
Product specification
Dual 2-to-4 line decoder/demultiplexer
74LVC139
handbook, halfpage
1
handbook, halfpage
1E 2 3 1Y0 1A0 1A1 1Y1 1Y2 1Y3 14 13 2Y0 2A0 2A1 2E 2Y1 2Y2 2Y3
2
4 5 6 7 12 11 10 9
3 1
DX 0 0 01 G 3 1 2 3 DX 0 01 G 3 1 2 0 3
4 5 6 7 2 3 1 1 2 EN
X/Y 0 1 2 3 X/Y 0 1 2 EN 1 2 3
4 5 6 7
12 11 10 9 14 13 15
12 11 10 9
MNA781
14 13 15
15
(a)
MNA779
(b)
b) decoder.
a) demultiplexer.
Fig.3 Logic symbol.
Fig.4 Logic symbol (IEEE/IEC).
handbook, halfpage
1Y0 2 3 1A0 1A1 DECODER 1Y1 1Y2 1Y3 1 1E
4 5 6 7
14 13
2A0 2A1 DECODER
2Y0 12 2Y1 11 2Y2 10 2Y3 9
15
2E
MNA780
Fig.5 Functional diagram.
2003 May 19
5
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