|
|
Part: 74LVC1G74
Category:
Logic
-> Flip-Flops
Description: Single D-type Flip-flop With Set And Reset; Positive Edge Trigger<<<>>>the 74LVC1G74 is a High-performance, Low-voltage, Si-gate CMOS Device, Superior to MOSt Advanced CMOS Compatible TTL Families. <<<>>><<<>>>The 74LVC1G74 is a Single Positive Edge Triggered D-type Flip-flop With Individual Data (D) Inputs, Clock (CP) Inputs, Set (SD) And (RD) Inputs, And Complementary Q And Q Outputs. <<<>>><<<>>>This Device is Fully Specified For Partial Power Down Applications Using Ioff. The Ioff Circuitry Disables The Output, Preventing Damaging Backflow Current Through The Device When it is Powered Down. <<<>>><<<>>>The Set And Reset Are Asynchronous Active Low Inputs And Operate Independently of The Clock Input. Information on The Data Input is Transferred to The Q Output on The Low-to-high Transition of The Clock Pulse. The D Inputs Must be Stable One Set-up Time Prior to The Low-to-high Clock Transition, For Predictable Operation. <<<>>><<<>>>Schmitt-trigger Action at All Inputs Makes The Circuit Highly Tolerant to Slower Input Rise And Fall Times. <<<>>><<<>>> <<<>>> Features Wide Supply Voltage Range From 1.65 to 5.5 V <<<>>>5 V Tolerant Inputs For Interfacing With 5 V Logic <<<>>>High Noise Immunity <<<>>>Complies With Jedec Standard: <<<>>>JESD8-7 (1.65 to 1.95 V) <<<>>>JESD8-5 (2.3 to 2.7 V) <<<>>>JESD8B/JESD36 (2.7 to 3.6 V). <<<>>>+-24 ma Output Drive (VCC = 3.0 V) <<<>>>ESD Protection: <<<>>>HBM EIA/JESD22-A114-A Exceeds 2000 V <<<>>>MM EIA/JESD22-A115-A Exceeds 200 V. <<<>>>CMOS Low Power Consumption <<<>>>Latch-up Performance Exceeds 250 ma <<<>>>Direct Interface With TTL Levels <<<>>>Inputs Accept Voltages up to 5 V <<<>>>SOT505-2 And SOT765-1 Package <<<>>>Specified From -40 to +85 Cel And -40 to +125 Cel.
Company: Philips Semiconductors
Datasheet: Download 74LVC1G74 datasheet File size : 132 kB
Request For quote: Find where to buy 74LVC1G74
Datasheet text preview:
INTEGRATED CIRCUITS
DATA SHEET
74LVC1G74 Single D-type flip-flop with set and reset; positive edge trigger
Product specification 2004 Feb 02
Philips Semiconductors
Product specification
Single D-type flip-flop with set and reset; positive edge trigger
FEATURES · Wide supply voltage range from 1.65 to 5.5 V · 5 V tolerant inputs for interfacing with 5 V logic · High noise immunity · Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V). · ±24 mA output drive (VCC = 3.0 V) · ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. · CMOS low power consumption · Latch-up performance exceeds 250 mA · Direct interface with TTL levels · Inputs accept voltages up to 5 V · SOT505-2 and SOT765-1 package · Specified from -40 to +85 °C and -40 to +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf 2.5 ns. SYMBOL tPHL/tPLH CP to Q, Q SD to Q, Q RD to Q, Q fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; (CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. maximum clock frequency input capacitance power dissipation capacitance VCC = 3.3 V; notes 1 and 2 PARAMETER propagation delay CL = 50 pF; VCC = 3.3 V CL = 50 pF; VCC = 3.3 V CL = 50 pF; VCC = 3.3 V CL = 50 pF; VCC = 3.3 V 3.5 3.0 3.0 280 4.0 15 CONDITIONS DESCRIPTION
74LVC1G74
The 74LVC1G74 is a high-performance, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs, and complementary Q and Q outputs. This device is fully specified for partial power down applications using Ioff. The Ioff circuitry disables the output, preventing damaging backflow current through the device when it is powered down. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and fall times.
TYPICAL ns ns ns
UNIT
MHz pF pF
2004 Feb 02
2
Philips Semiconductors
Product specification
Single D-type flip-flop with set and reset; positive edge trigger
FUNCTION TABLES Table 1 See note 1. INPUT SD L H L Table 2 See note 1. INPUT SD H H Note to Tables 1 and 2 1. H = HIGH voltage level; L = LOW voltage level; X = don't care; = LOW-to-HIGH CP transition; Qn+1 = state after the next LOW-to-HIGH CP transition. ORDERING INFORMATION PACKAGE TYPE NUMBER 74LVC1G74DP 74LVC1G74DC PINNING PIN 1 2 3 4 5 6 7 8 SYMBOL CP D Q GND Q RD SD VCC DESCRIPTION clock input (LOW-to-HIGH, edge-triggered) data input complement flip-flop output ground (0 V) true flip-flop output asynchronous reset-direct input (active LOW) asynchronous set-direct input (active LOW) supply voltage
Q3 GND 4
MNB138
74LVC1G74
OUTPUT CP X X X D X X X Q H L H Q L H H
RD H L L
OUTPUT CP D L H Qn+1 L H Qn+1 H L
RD H H
TEMPERATURE RANGE -40 to +125 °C -40 to +125 °C
PINS 8 8
PACKAGE TSSOP8 VSSOP8
MATERIAL plastic plastic
CODE SOT505-2 SOT765-1
MARKING V74 V74
handbook, halfpage
CP 1 D2
8 VCC 7 SD
74
6 RD 5Q
Fig.1 Pin configuration.
2004 Feb 02
3
Philips Semiconductors
Product specification
Single D-type flip-flop with set and reset; positive edge trigger
74LVC1G74
handbook, halfpage
7 SD 2 1 D CP SD D CP FF Q RD RD 6
MNB139
Q
Q
5
handbook, halfpage
7 1 2
S C1 1D R
MNB140
5
Q
3
6
3
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
handbook, full pagewidth
Q C C
C C D C RD
C C Q C
SD
MNA421
CP
C C
Fig.4 Logic diagram.
2004 Feb 02
4
Philips Semiconductors
Product specification
Single D-type flip-flop with set and reset; positive edge trigger
RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO Tamb tr, tf PARAMETER supply voltage input voltage output voltage ambient temperature input rise and fall times VCC = 1.65 to 2.7 V VCC = 2.7 to 5.5 V active mode VCC = 0 V; Power-down mode CONDITIONS 0 0 0 -40 0 0 MIN. 1.65
74LVC1G74
MAX. 5.5 5.5 VCC 5.5 +125 20 10 V V V V
UNIT
°C ns/V ns/V
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO IO ICC, IGND Tstg PD Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. PARAMETER supply voltage input diode current input voltage output diode current output voltage output source or sink current VCC or GND current storage temperature power dissipation Tamb = -40 to +125 °C VI VCC or VO < 0 active mode; notes 1 and 2 VO = 0 to VCC CONDITIONS - -0.5 - -0.5 - - -65 - MIN. -0.5 MAX. +6.5 -50 +6.5 ±50 +6.5 ±50 ±100 +150 250 V mA V mA V mA mA °C mW UNIT
VCC + 0.5 V
Power-down mode; notes 1 and 2 -0.5
2004 Feb 02
5
Others parts begin by 74
74-1 74-2 74-3 74-4 74-5 74-6 74-7 74-8 74-9 74-10 74-11 74-12 74-13 74-14 74-15 74-16 74-17 74-18 74-19 74-20 74-21 74-22 74-23 74-24 74-25 74-26 74-27 74-28 74-29 74-30 74-31 74-32 74-33 74-34 74-35 74-36 74-37 74-38 74-39 74-40 74-41 74-42 74-43 74-44 74-45 74-46 74-47 74-48 74-49 74-50 74-51 74-52 74-53 74-54 74-55 74-56 74-57 74-58 74-59 74-60 74-61 74-62
|
|
|
