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Details, datasheet, quote on part number:74LVC1G80
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Datasheet text preview:
INTEGRATED CIRCUITS
DATA SHEET
74LVC1G80 Single D-type flip-flop; positive-edge trigger
Product specification Supersedes data of 2003 Jan 30 2003 May 26
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
FEATURES · Wide supply voltage range from 1.65 to 5.5 V · High noise immunity · Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V). · ±24 mA output drive (VCC = 3.0 V) · ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. · CMOS low power consumption · Latch-up performance exceeds 250 mA · Direct interface with TTL levels · Inputs accept voltages up to 5 V · Multiple package options · Specified from -40 to +85 °C and -40 to +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf 2.5 ns. SYMBOL tPHL/tPLH PARAMETER propagation delay CP to Q CONDITIONS VCC = 1.8 V; CL = 30 pF; RL = 1 k VCC = 2.5 V; CL = 30 pF; RL = 500 VCC = 2.7 V; CL = 50 pF; RL = 500 VCC = 3.3 V; CL = 50 pF; RL = 500 VCC = 5.0 V; CL = 50 pF; RL = 500 CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in volts; N = total switching outputs; (CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. input capacitance power dissipation capacitance per buffer VCC = 3.3 V; notes 1 and 2 DESCRIPTION
74LVC1G80
The 74LVC1G80 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. This feature allows the use of this device in a mixed 3.3 and 5 V environment. This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74LVC1G80 provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
TYPICAL 3.4 2.3 2.5 2.4 1.8 5.0 17
UNIT ns ns ns ns ns pF pF
2003 May 26
2
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
FUNCTION TABLE See note 1. INPUT CP L Note 1. H = HIGH voltage level; L = LOW voltage level; = LOW-to-HIGH CP transition; X = don't care; D L H X
74LVC1G80
OUTPUT Q H L q
q = lower case letter indicates the state of referenced input, one set-up time prior to the LOW-to-HIGH CP transition. ORDERING INFORMATION PACKAGE TYPE NUMBER 74LVC1G80GW 74LVC1G80GV PINNING PIN 1 2 3 4 5 D CP GND Q VCC SYMBOL data input D clock pulse input CP ground (0 V) data output Q supply voltage DESCRIPTION TEMPERATURE RANGE -40 to +125 °C -40 to +125 °C PINS 5 5 PACKAGE SC-88A SC-74A MATERIAL plastic plastic CODE SOT353 SOT753 MARKING VT V80
2003 May 26
3
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G80
handbook, halfpage handbook, halfpage
D1 CP 2 GND 3
MNA648
5 VCC
1
D
Q
4
80
4 Q 2 CP
MNA649
Fig.1 Pin configuration.
Fig.2 Logic symbol.
handbook, halfpage
1 2
MNA650
4
Fig.3 IEE/IEC logic symbol.
2003 May 26
4
Philips Semiconductors
Product specification
Single D-type flip-flop; positive-edge trigger
74LVC1G80
handbook, full pagewidth
CP
C C C C
D
TG C
TG C
Q
MNA651
C
C
TG
TG
C
C
Fig.4 Logic diagram.
2003 May 26
5
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