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Details, datasheet, quote on part number:74LVC374A
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| Part: | 74LVC374A |
| Category: | Logic => Flip-Flops => CMOS/BiCMOS->LVC/ALVC/VCX Family->Low Voltage |
| Description: | Octal D-type Flip-flop With 5-volt Tolerant Inputs/outputs; Positive Edge-trigger; 3-state |
| Company: | Philips Semiconductors |
| Datasheet: | Download 74LVC374A datasheet File size : 115 kB |
| Request For quote: | Find where to buy 74LVC374A
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Datasheet text preview:
INTEGRATED CIRCUITS
74LVC374A Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State)
Product specification 1998 Jul 29
Philips Semiconductors
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State)
74LVC374A
FEATURES
· 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic · Supply voltage range of 2.7V to 3.6V · Complies with JEDEC standard no. 8-1A · CMOS low power consumption · Direct interface with TTL levels · High impedance when VCC = 0V · 8-bit positive edge-triggered register · Independent register and 3-State buffer operation
DESCRIPTION
The 74LVC374A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment. The 74LVC374A is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-State outputs for bus-oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The eight flip-flops will store the state of their individual D-inputs that meet the setup and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the eight flip-flops is available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The '374' is functionally identical to the '574', but the '574' has a different pin arrangement.
QUICK REFERENCE DATA
GND = 0V; Tamb =25°C; tr = tf v 2.5ns SYMBOL tPHL/tPLH fmax CI CP D PARAMETER Propagation delay CP to Qn maximum clock frequency Input capacitance Power dissipation capacitance per flip-flop Notes 1 and 2 CONDITIONS CL = 50pF VCC = 3.3V TYPICAL 4.8 150 5.0 20 UNIT ns MHz pF pF
NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD x VCC2 x fi + S (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL x VCC2 x fo) = sum of outputs. 2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES 20-Pin Plastic Shrink Small Outline (SO) 20-Pin Plastic Shrink Small Outline (SSOP) Type II 20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I TEMPERATURE RANGE 40°C to +85°C 40°C to +85°C 40°C to +85°C OUTSIDE NORTH AMERICA 74LVC374A D 74LVC374A DB 74LVC374A PW NORTH AMERICA 74LVC374A D 74LVC374A DB 7LVC374APW DH PKG. DWG. # SOT163-1 SOT339-1 SOT360-1
1998 Jul 29
2
853-1861 19802
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State)
74LVC374A
PIN CONFIGURATION
LOGIC SYMBOL (IEEE/IEC)
11 C1 EN1
OE Q0 D0 D1 Q1 Q2 D2 D3 Q3
1 2 3 4 5 6 7 8 9
20 19 18 17 16 15 14 13 12 11
VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP
1
3 4 7 8 13 14 17 18
1D
2 5 6 9 12 15 16 19
GND 10
SA00389
SA00391
PIN DESCRIPTION
PIN NUMBER 1 3, 4, 7, 8, 13, 14, 17, 18 2, 5, 6, 9, 12, 15, 16, 19 11 10 20 SYMBOL OE D0-D7 Q0-Q7 CP GND VCC FUNCTION Output enable input (active-Low) Data inputs 3-state flip-flop outputs Clock input (LOW-to-HIGH, edge-triggered) Ground (0V) Positive supply voltage
FUNCTIONAL DIAGRAM
3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7 CP OE FF1 to FF8 3-State OUTPUTS
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
LOGIC SYMBOL
11
11 1
SA00392
3 4 7 8 13 14 17 18 D0 D1 D2 D3 D4 D5 D6 D7 OE CP Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19
1
SA00390
1998 Jul 29
3
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State)
74LVC374A
LOGIC DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7
D CP FF1
Q
D CP FF2
Q
D CP FF3
Q
D CP
Q
D CP FF5
Q
D CP FF6
Q
D CP FF7
Q
D CP FF8
Q
FF4
CP
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
SA00393
FUNCTION TABLE
INPUTS OPERATING MODES MODES Load and read register Load register and disable outputs H h L l Z ° OE L L H H LE ° ° ° ° Dn l h l h INTERNAL FLIP-FLOPS FLIP-FLOPS L H L H OUTPUTS Q0 to Q7 L H Z Z
= HIGH voltage level = HIGH voltage level one setup time prior to the LOW-to-HIGH CP transition = LOW voltage level = LOW voltage level one setup time prior to the LOW-to-HIGH CP transition = High impedance OFF-state = LOW-to-HIGH clock transition
1998 Jul 29
4
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State)
74LVC374A
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL PARAMETER DC supply voltage (for max. speed performance) VCC VI VO Tamb tr, tf DC supply voltage (for low-voltage applications) DC input voltage range DC output voltage range; output HIGH or LOW state DC output voltage range; output 3-State Operating ambient temperature range in free-air Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V CONDITIONS MIN 2.7 1.2 0 0 0 40 0 0 MAX 3.6 V 3.6 5.5 VCC 5.5 +85 20 10 °C ns/V V V UNIT
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC IIK VI IOK VO IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC input voltage DC output diode current DC output voltage; output HIGH or LOW state DC output voltage; output 3-State DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package plastic mini-pack (SO) plastic shrink mini-pack (SSOP and TSSOP) above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K VI t0 Note 2 VO uVCC or VO t 0 Note 2 Note 2 VO = 0 to VCC CONDITIONS RATING 0.5 to +6.5 50 0.5 to +6.5 "50 0.5 to VCC +0.5 0.5 to 6.5 "50 "100 65 to +150 500 500 UNIT V mA V mA V mA mA °C
mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Jul 29
5
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