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Details, datasheet, quote on part number:74LVC374APW
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| Part: | 74LVC374APW |
| Category: | Logic => Flip-Flops |
| Description: | 74LVC374A; Octal D-type Flip-flop With 5 V Tolerant Inputs/outputs; Positive Edge-trigger; 3-state;; Package: SOT360-1 (TSSOP20) |
| Company: | Philips Semiconductors |
| Datasheet: | Download 74LVC374APW datasheet File size : 120 kB |
| Request For quote: | Find where to buy 74LVC374APW
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Datasheet text preview:
INTEGRATED CIRCUITS
DATA SHEET
74LVC374A Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state
Product specification Supersedes data of 1998 July 29 2003 May 14
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state
FEATURES · 5 V tolerant inputs/outputs; for interfacing with 5 V logic · Wide supply voltage range from 1.2 to 3.6 V · Inputs accept voltages up to 5.5 V · CMOS low power consumption · Direct interface with TTL levels · High-impedance when VCC = 0 V · 8-bit positive edge-triggered register · Independent register and 3-state buffer operation · Complies with JEDEC standard no. 8-1A · ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. · Specified from -40 to +85 °C and -40 to +125 °C. DESCRIPTION
74LVC374A
The 74LVC374A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. This feature allows the use of these devices as translators in a mixed 3.3 and 5 V environment. The 74LVC374A is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock input (CP) and an outputs enable input (OE) are common to all flip-flops. The eight flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When pin OE is LOW, the contents of the eight flip-flops is available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The 74LVC374A is functionally identical to the 74LVC574A, but the 74LVC574A has a different pin arrangement.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf 2.5 ns. SYMBOL tPHL/tPLH fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; (CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. PARAMETER propagation delay CP to Qn maximum clock frequency input capacitance power dissipation capacitance per gate VCC = 3.3 V; notes 1 and 2 CONDITIONS CL = 50 pF; VCC = 3.3 V TYPICAL 2.7 100 4.0 15 ns MHz pF pF UNIT
2003 May 14
2
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state
FUNCTION TABLE See note 1. INPUT OPERATING MODE OE Load and read register Load register and disable outputs Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; Z = high-impedance OFF-state; = LOW-to-HIGH clock transition. ORDERING INFORMATION PACKAGE TYPE NUMBER 74LVC374AD 74LVC374ADB 74LVC374APW 74LVC374ABQ PINNING PIN 1 2 3 4 5 6 7 8 9 10 SYMBOL OE Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND DESCRIPTION output enable input (active LOW) 3-state flip-flop output data input data input 3-state flip-flop output 3-state flip-flop output data input data input 3-state flip-flop output ground (0 V) 12 13 14 15 16 17 18 19 20 Q4 D4 D5 Q5 Q6 D6 D7 Q7 VCC TEMPERATURE RANGE -40 to +125 °C -40 to +125 °C -40 to +125 °C -40 to +125 °C PINS 20 20 20 20 PACKAGE SO20 SSOP20 TSSOP20 DHVQFN20 MATERIAL plastic plastic plastic plastic L L H H CP Dn l h l h INTERNAL FLIP-FLOP L H L H
74LVC374A
OUTPUT Qn L H Z Z
CODE SOT163-1 SOT339-1 SOT360-1 SOT764-1
PIN 11
SYMBOL CP
DESCRIPTION clock input (LOW-to-HIGH, edge-triggered) 3-state flip-flop output data input data input 3-state flip-flop output 3-state flip-flop output data input data input 3-state flip-flop output supply voltage
2003 May 14
3
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state
74LVC374A
handbook, halfpage
OE 1
VCC 20 19 18 17 16 Q7 D7 D6 Q6 Q5 D5 D4 Q4
handbook, halfpage
OE 1 Q0 2 D0 3 D1 4 Q1 5
20 VCC 19 Q7 18 D7 17 D6 16 Q6
Q0 D0 D1 Q1 Q2 D2 D3 Q3
2 3 4 5
374
Q2 6 D2 7 D3 8 Q3 9 GND 10
MNA194
15 Q5 14 D5 13 D4 12 Q4 11 CP
GND(1)
6 7 8 9 10 Top view GND 11 CP
MNB001
15 14 13 12
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
Fig.1 Pin configuration SO20 and (T)SSOP20.
Fig.2 Pin configuration DHVQFN20.
handbook, halfpage
1 11
EN C1 2 5 6 9 12 15 16 19
MNA196
handbook, halfpage
11 3 4 7 8 13 14 17 18 CP D0 D1 D2 D3 D4 D5 D6 D7 OE 1
MNA891
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
3 4 7 8 13 14 17 18
1D
Fig.3 Logic symbol.
Fig.4 Logic symbol (IEEE/IEC).
2003 May 14
4
Philips Semiconductors
Product specification
Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state
74LVC374A
handbook, halfpage
3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7 FF1 to FF8 3-STATE OUTPUTS
Q0 Q1 Q2 Q3
2 5 6 9
Q4 12 Q5 15 Q6 16 Q7 19
11 CP 1 OE
MNA892
Fig.5 Functional diagram.
D0
D1
D2
D3
D4
D5
D6
D7
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
D CP
Q
FF1
FF2
FF3
FF4
FF5
FF6
FF7
FF8
CP OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
MNA893
Fig.6 Logic diagram.
2003 May 14
5
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