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Details, datasheet, quote on part number:74LVC38A
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| Part: | 74LVC38A |
| Category: | Logic => Gates => NAND Gates |
| Description: | 74LVC38A; Quad 2-input NAND Gate (open Drain);; Package: SOT108-1 (SO14), SOT337-1 (SSOP14), SOT402-1 (TSSOP14) |
| Company: | Philips Semiconductors |
| Datasheet: | Download 74LVC38A datasheet File size : 87 kB |
| Request For quote: | Find where to buy 74LVC38A
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Datasheet text preview:
INTEGRATED CIRCUITS
DATA SHEET
74LVC38A Quad 2-input NAND gate (open drain)
Product specification 2002 Apr 08
Philips Semiconductors
Product specification
Quad 2-input NAND gate (open drain)
FEATURES · 5 V tolerant inputs for interfacing with 5 V logic · Wide supply voltage range from 1.2 to 3.6 V · CMOS low power consumption · Direct interface with TTL levels · Open-drain outputs · Inputs accept voltages up to 5.5 V · Complies with JEDEC standard no. 8-1A · Specified from -40 to +85 °C and -40 to +125 °C. DESCRIPTION
74LVC38A
The 74LVC38A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 and 5 V environment. The 74LVC38A provides the 2-input NAND function. The outputs of the 74LVC38A devices are open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf 2.5 ns. SYMBOL tPZL tPLZ CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; (CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. ORDERING INFORMATION TYPE NUMBER 74LVC38AD 74LVC38ADB 74LVC38APW TEMPERATURE RANGE -40 to +125 °C -40 to +125 °C -40 to +125 °C PACKAGES PINS 14 14 14 PACKAGE SO SSOP TSSOP MATERIAL plastic plastic plastic CODE SOT108-1 SOT337-1 SOT402-1 PARAMETER propagation delay nA, nB to nY propagation delay nA, nB to nY input capacitance power dissipation capacitance per gate VCC = 3.3 V; notes 1 and 2 CONDITIONS CL = 50 pF; VCC = 3.3 V CL = 50 pF; VCC = 3.3 V TYPICAL 2.2 2.8 4.0 5.5 UNIT ns ns pF pF
2002 Apr 08
2
Philips Semiconductors
Product specification
Quad 2-input NAND gate (open drain)
FUNCTION TABLE See note 1. INPUTS nA L L H H Note 1. H = HIGH voltage level; L = LOW voltage level: Z = high-impedance OFF-state. PINNING PIN 1, 4, 9, 12 2, 5, 10, 13 3, 6, 8, 11 7 14 1A to 4A 1B to 4B 1Y to 4Y GND VCC SYMBOL data inputs data inputs data outputs ground (0 V) supply voltage nB L H L H
74LVC38A
OUTPUTS nY Z Z Z L
DESCRIPTION
handbook, halfpage
1A 1B 1Y 2A 2B 2Y GND
1 2 3 4 5 6 7
MNA696
14 VCC 13 4B 12 4A
handbook, halfpage
1 2 4 5 9 10 12 13
1A 1B 2A 2B 3A 3B 4A 4B
1Y
3
2Y
6
38
11 4Y 10 3B 9 3A
3Y
8
4Y
11
8 3Y
MNA697
Fig.1 Pin configuration.
Fig.2 Logic symbol.
2002 Apr 08
3
Philips Semiconductors
Product specification
Quad 2-input NAND gate (open drain)
74LVC38A
handbook, halfpage
1 2 4 5 9 10 12 13
&
3
handbook, halfpage
&
6 A
Y
&
8 B GND
MNA699
&
11
MNA698
Fig.3 Logic symbol (IEEE/IEC).
Fig.4 Logic diagram (one gate).
2002 Apr 08
4
Philips Semiconductors
Product specification
Quad 2-input NAND gate (open drain)
RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO Tamb tr, tf PARAMETER supply voltage input voltage output voltage operating ambient temperature input rise and fall times VCC = 1.2 to 2.7 V VCC = 2.7 to 3.6 V CONDITIONS for maximum speed performance for low voltage applications MIN. 2.7 1.2 0 0 -40 0 0
74LVC38A
MAX. 3.6 3.6 5.5 VCC +125 20 10 V V V V
UNIT
°C ns/V ns/V
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO IO IGND, ICC Tstg Ptot PARAMETER supply voltage input diode current input voltage output diode current output voltage output source or sink current VCC or GND current storage temperature power dissipation per package SO package SSOP and TSSOP packages Note 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. above 70 °C derate linearly with 8 mW/K above 60 °C derate linearly with 5.5 mW/K - - 500 500 mW mW VI VCC or VO < 0 note 1 VO = 0 to VCC CONDITIONS - -0.5 - -0.5 - - -65 MIN. -0.5 MAX. +6.5 -50 +6.5 ±50 ±50 ±100 +150 V mA V mA mA mA °C UNIT
VCC + 0.5 V
2002 Apr 08
5
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