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Details, datasheet, quote on part number:74LVC3G04
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| Part: | 74LVC3G04 |
| Category: | Logic => Gates => Inverters Gates |
| Description: | The 74LVC3G04 is a High-performance, Low-power, Low-voltage, Si-gate CMOS Device And Superior to MOSt Advanced CMOS Compatible TTL Families. <<<>>><<<>>>Inputs CAN be Driven From Either 3.3 V or 5 V Devices. This Feature Allows The Use of These Devices as Translators in a Mixed 3.3 V And 5 V Environment. <<<>>><<<>>>This Device is Fully Specified For Partial Power-down Applications Using Ioff . The Ioff Circuitry Disables The Output, Preventing The Damaging Backflow Current Through The Device When it is Powered Down. <<<>>><<<>>>The 74LVC3G04 Provides Three Inverting Buffers. <<<>>><<<>>> <<<>>> Features Wide Supply Voltage Range From 1.65 V to 5.5 V <<<>>>5 V Tolerant Outputs For Interfacing With 5 V Logic <<<>>>High Noise Immunity <<<>>>Complies With Jedec Standard: <<<>>>JESD8-7 (1.65 V to 1.95 V) <<<>>>JESD8-5 (2.3 V to 2.7 V) <<<>>>JESD8-B/JESD36 (2.7 V to 3.6 V). <<<>>>ESD Protection: <<<>>>HBM EIA/JESD22-A114-B Exceeds 2000 V <<<>>>MM EIA/JESD22-A115-A Exceeds 200 V. <<<>>>+-24 ma Output Drive (VCC = 3.0 V) <<<>>>CMOS Low Power Consumption <<<>>>Latch-up Performance Exceeds 250 ma <<<>>>Direct Interface With TTL Levels <<<>>>SOT505-2 And SOT765-1 Package <<<>>>Specified From -40 Cel to +85 Cel And -40 Cel to +125 Cel. |
| Company: | Philips Semiconductors |
| Datasheet: | Download 74LVC3G04 datasheet File size : 76 kB |
| Request For quote: | Find where to buy 74LVC3G04
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Datasheet text preview:
74LVC3G04
Triple inverter
Rev. 01 -- 4 May 2004 Product data sheet
1. General description
The 74LVC3G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. This device is fully specified for par tial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74LVC3G04 provides three inverting buffers.
2. Features
s s s s Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant outputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: x JESD8-7 (1.65 V to 1.95 V) x JESD8-5 (2.3 V to 2.7 V) x JESD8-B/JESD36 (2.7 V to 3.6 V). ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V. ±24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels SOT505-2 and SOT765-1 package Specified from -40 °C to +85 °C and -40 °C to +125 °C.
s
s s s s s s
Philips Semiconductors
74LVC3G04
Triple inverter
3. Quick reference data
Table 1: Quick reference data GND = 0 V; Tamb = 25 °C. Symbol tPHL, tPLH Parameter propagation delay inputs nA to output nY Conditions VCC = 1.8 V; CL = 30 pF; RL = 1 k VCC = 2.5 V; CL = 30 pF; RL = 500 VCC = 2.7 V; CL = 50 pF; RL = 500 VCC = 3.3 V; CL = 50 pF; RL = 500 VCC = 5.0 V; CL = 50 pF; RL = 500 CI CPD
[1]
Min -
Typ 3.5 2.2 2.7 2.7 1.9 2.5 13.5
Max -
Unit ns ns ns ns ns pF pF
input capacitance power dissipation capacitance VCC = 3.3 V
[1] [2]
-
CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = total load switching outputs; (CL × VCC2 × fo) = sum of the outputs. The condition is VI = GND to VCC.
[2]
4. Ordering information
Table 2: Ordering information Package Temperature range Name 74LVC3G04DP -40 °C to +125 °C 74LVC3G04DC -40 °C to +125 °C TSSOP8 VSSOP8 Description plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm Version SOT505-2 Type number
plastic very thin shrink small outline package; 8 leads; body SOT765-1 width 2.3 mm
9397 750 13075
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 -- 4 May 2004
2 of 13
Philips Semiconductors
74LVC3G04
Triple inverter
5. Functional diagram
1 1 1A 1Y 7
1
7
3
2A
2Y
5
3
1
5
A
Y
mna110
6
3A
3Y
2 6 1 2
mna720 mna721
Fig 1. Logic symbol.
Fig 2. IEC logic symbol.
Fig 3. Logic diagram (one driver).
6. Pinning information
6.1 Pinning
1A 3Y 2A GND
1 2 3 4
mna719
8
VCC 1Y 3A 2Y
04
7 6 5
Fig 4. Pin configuration.
6.2 Pin description
Table 3: Pin 1 2 3 4 5 6 7 8 Pin description Symbol 1A 3Y 2A GND 2Y 3A 1Y VCC Description data input data output data input ground (0 V) data output data input data output supply voltage
9397 750 13075
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 -- 4 May 2004
3 of 13
Philips Semiconductors
74LVC3G04
Triple inverter
7. Functional description
7.1 Function table
Table 4: Input nA L H
[1] H = HIGH voltage level; L = LOW voltage level.
Function table
[1]
Output nY H L
8. Limiting values
Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC, IGND Tstg Ptot
[1] [2]
Parameter supply voltage input diode current input voltage output diode current output voltage output current VCC or GND current storage temperature power dissipation
Conditions VI < 0 V
[1]
Min -0.5 -0.5 [1] [2] [1] [2]
Max +6.5 -50 +6.5 ±50 +6.5 ±50 ±100 +150 300
Unit V mA V mA V mA mA °C mW
VO > VCC or VO < 0 V active mode Power-down mode VO = 0 V to VCC
-0.5 -0.5 -65
VCC + 0.5 V
Tamb = -40 °C to +125 °C
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
9. Recommended operating conditions
Table 6: Symbol VCC VI VO Recommended operating conditions Parameter supply voltage input voltage output voltage active mode Power-down mode; VCC = 0 V Tamb tr, tf operating ambient temperature input rise and fall times VCC = 1.65 V to 2.7 V VCC = 2.7 V to 5.5 V Conditions Min 1.65 0 0 0 -40 0 0 Typ Max 5.5 5.5 VCC 5.5 +125 20 10 Unit V V V V °C ns/V ns/V
9397 750 13075
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 -- 4 May 2004
4 of 13
Philips Semiconductors
74LVC3G04
Triple inverter
10. Static characteristics
Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = -40 °C to +85 VIH °C [1] VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL LOW-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V VOH HIGH-level output voltage VI = VIH or VIL IO = -100 µA; VCC = 1.65 V to 5.5 V IO = -4 mA; VCC = 1.65 V IO = -8 mA; VCC = 2.3 V IO = -12 mA; VCC = 2.7 V IO = -24 mA; VCC = 3.0 V IO = -32 mA; VCC = 4.5 V ILI Ioff ICC ICC CI VIH input leakage current power-off leakage current quiescent supply current VI = 5.5 V or GND; VCC = 5.5 V VI or VO = 5.5 V; VCC = 0 V VI = VCC or GND; IO = 0 A; VCC = 5.5 V VCC - 0.1 1.2 1.9 2.2 2.3 3.8 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V 0.65 × VCC 1.7 2.0 0.7 × VCC ±0.1 ±0.1 0.1 5 2.5 ±5 ±10 10 500 V V V V V V µA µA µA µA pF V V V V 0.1 0.45 0.3 0.4 0.55 0.55 V V V V V V 0.65 × VCC 1.7 2.0 0.7 × VCC 0.35 × VCC 0.7 0.8 0.3 × VCC V V V V V V V V HIGH-level input voltage Conditions Min Typ Max Unit
additional quiescent VI = VCC - 0.6 V; IO = 0 A; supply current per pin VCC = 2.3 V to 5.5 V input capacitance HIGH-level input voltage
Tamb = -40 °C to +125 °C
9397 750 13075
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 -- 4 May 2004
5 of 13
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