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Details, datasheet, quote on part number:74LVC3G14DP
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| Part: | 74LVC3G14DP |
| Category: | Logic => Schmitt Triggers |
| Description: | Triple Inverting Schmitt Trigger With 5 V Tolerant Input <<<>>>The 74LVC3G14 is a High-performance, Low-power, Low-voltage, Si-gate CMOS Device And Superior to MOSt Advanced CMOS Compatible TLL-families. <<<>>><<<>>>Inputs CAN be Driven From Either 3.3 V or 5 V Devices. This Feature Allows The Use of This Device as Translator in a Mixed 3.3 V And 5 V Environment. <<<>>><<<>>>This Device is Fully Specified For Partial Power-down Applications Using Ioff . The Ioff Circuitry Disables The Output, Preventing The Damaging Backflow Current Through The Device When it is Powered Down. <<<>>><<<>>>The 74LVC3G14 Provides Three Inverting Buffers With Schmitt-trigger Action. It is Capable of Transforming Slowly Changing Input Signals Into Sharply Defined, Jitter-free Output Signals. <<<>>><<<>>> <<<>>> Features Wide Supply Voltage Range From 1.65 V to 5.5 V <<<>>>5 V Tolerant Input/output For Interfacing With 5 V Logic <<<>>>High Noise Immunity <<<>>>Complies With Jedec Standard: <<<>>>JESD8-7 (1.65 V to 1.95 V) <<<>>>JESD8-5 (2.3 V to 2.7 V) <<<>>>JESD8-B/JESD36 (2.7 V to 3.6 V). <<<>>>ESD Protection: <<<>>>HBM EIA/JESD22-A114-B Exceeds 2000 V <<<>>>MM EIA/JESD22-A115-A Exceeds 200 V. <<<>>>+-24 ma Output Drive (VCC = 3.0 V) <<<>>>CMOS Low Power Consumption <<<>>>Latch-up Performance Exceeds 250 ma <<<>>>Direct Interface With TLL Levels <<<>>>SOT505-2 And SOT765-1 Package <<<>>>Specified From -40 Cel to +85 Cel And -40 Cel to +125 Cel. |
| Company: | Philips Semiconductors |
| Datasheet: | Download 74LVC3G14DP datasheet File size : 87 kB |
| Request For quote: | Find where to buy 74LVC3G14DP
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Datasheet text preview:
74LVC3G14
Triple inverting Schmitt trigger with 5 V tolerant input
Rev. 01 -- 10 May 2004 Product data sheet
1. General description
The 74LVC3G14 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TLL-families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device as translator in a mixed 3.3 V and 5 V environment. This device is fully specified for par tial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74LVC3G14 provides three inverting buffers with Schmitt-trigger action. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
2. Features
s s s s Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: x JESD8-7 (1.65 V to 1.95 V) x JESD8-5 (2.3 V to 2.7 V) x JESD8-B/JESD36 (2.7 V to 3.6 V). ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V. ±24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TLL levels SOT505-2 and SOT765-1 package Specified from -40 °C to +85 °C and -40 °C to +125 °C.
s
s s s s s s
3. Applications
s Wave and pulse shaper for highly noisy environment s Astable multivibrator s Monostable multivibrator.
Philips Semiconductors
74LVC3G14
Triple inverting Schmitt trigger with 5 V tolerant input
4. Quick reference data
Table 1: Quick reference data GND = 0 V; Tamb = 25 °C. Symbol Parameter Conditions Min VCC = 3.3 V
[1] [2]
Typ 4.2 3.0 3.8 3.2 2.4 3.5 18.1
Max -
Unit ns ns ns ns ns pF pF
tPHL, tPLH propagation delay input VCC = 1.8 V; nA to output nY CL = 30 pF; RL = 1 k VCC = 2.5 V; CL = 30 pF; RL = 500 VCC = 2.7 V; CL = 50 pF; RL = 500 VCC = 3.3 V; CL = 50 pF; RL = 500 VCC = 5.0 V; CL = 50 pF; RL = 500 CI CPD
[1]
input capacitance power dissipation capacitance per buffer
-
CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fj × N + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = total number of load switching outputs; (CL × VCC2 × fo) = sum of outputs. The conditions is VI = GND to VCC.
[2]
5. Ordering information
Table 2: Ordering information Package Temperature range Name 74LVC3G14DP 74LVC3G14DC -40 °C to +125 °C -40 °C to +125 °C TSSOP8 VSSOP8 Description plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm plastic very thin shrink small outline package; 8 leads; body width 2.3 mm Version SOT505-2 SOT765-1 Type number
6. Marking
Table 3: Marking Marking code V14 V14 Type number 74LVC3G14DP 74LVC3G14DC
9397 750 13139
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 -- 10 May 2004
2 of 16
Philips Semiconductors
74LVC3G14
Triple inverting Schmitt trigger with 5 V tolerant input
7. Functional diagram
1
7
1
1A
1Y
7 6 2
2
3Y
3A
6
3
2A
2Y
5
3
5
mna740
mna741
Fig 1. Logic symbol.
Fig 2. IEC logic symbol.
A
Y
mna025
Fig 3. Logic diagram (one Schmitt trigger).
8. Pinning information
8.1 Pinning
1A 3Y 2A GND
1 2 3 4
mna739
8
VCC 1Y 3A 2Y
3G14
7 6 5
Fig 4. Pin configuration.
8.2 Pin description
Table 4: Pin 1 2 3 4 5 6 7 8
9397 750 13139
Pin description Symbol 1A 3Y 2A GND 2Y 3A 1Y VCC Description data input data output data input ground (0 V) data output data input data output supply voltage
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 -- 10 May 2004
3 of 16
Philips Semiconductors
74LVC3G14
Triple inverting Schmitt trigger with 5 V tolerant input
9. Functional description
9.1 Function table
Table 5: Input nA L H
[1] H = HIGH voltage level; L = LOW voltage level.
Function table [1] Output nY H L
10. Limiting values
Table 6: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC, IGND Tstg PD
[1] [2]
Parameter supply voltage input diode current input voltage output diode current output voltage
Conditions VI < 0 V
[1]
Min -0.5 -0.5 [1] [2] [1] [2]
Max +6.5 -50 +6.5 ±50 VCC + 0.5 +6.5 ±50 ±100 +150 300
Unit V mA V mA V V mA mA °C mW
VO > VCC or VO < 0 V enable mode Power-down mode
-0.5 -0.5 -65
output source or sink VO = 0 V to VCC current VCC or GND current storage temperature power dissipation Tamb = -40 °C to +125 °C
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal condition.
11. Recommended operating conditions
Table 7: Symbol VCC VI VO Tamb Recommended operating conditions Parameter supply voltage input voltage output voltage operating ambient temperature Conditions Min 1.65 0 0 -40 Typ Max 5.5 5.5 VCC +125 Unit V V V °C
9397 750 13139
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 -- 10 May 2004
4 of 16
Philips Semiconductors
74LVC3G14
Triple inverting Schmitt trigger with 5 V tolerant input
12. Static characteristics
Table 8: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = -40 °C to +85 VOL °C [1] VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V VOH HIGH-level output voltage VI = VIH or VIL IO = -100 µA; VCC = 1.65 V to 5.5 V IO = -4 mA; VCC = 1.65 V IO = -8 mA; VCC = 2.3 V IO = -12 mA; VCC = 2.7 V IO = -24 mA; VCC = 3.0 V IO = -32 mA; VCC = 4.5 V ILI Ioff ICC ICC CI VOL input leakage current power-off leakage current additional quiescent supply per pin input capacitance LOW-level output voltage VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V VOH HIGH-level output voltage VI = VIH or VIL IO = -100 µA; VCC = 1.65 V to 5.5 V IO = -4 mA; VCC = 1.65 V IO = -8 mA; VCC = 2.3 V IO = -12 mA; VCC = 2.7 V IO = -24 mA; VCC = 3.0 V IO = -32 mA; VCC = 4.5 V ILI input leakage current VI = 5.5 V or GND; VCC = 5.5 V VI = 5.5 V or GND; VCC = 5.5 V VI or VO = 5.5 V; VCC = 0 V 1.2 1.9 2.2 2.3 3.8 0.95 1.7 1.9 2.0 3.4 ±0.1 ±0.1 0.1 5 3.5 0.1 0.45 0.3 0.4 0.55 0.55 ±5 ±10 10 500 0.1 0.70 0.45 0.60 0.80 0.80 ±20 V V V V V V µA V V V V V V V V V V V V µA µA µA µA pF V V V V V V LOW-level output voltage Conditions Min Typ Max Unit
VCC - 0.1 -
quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V VI = VCC - 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V
Tamb = -40 °C to +125 °C
VCC - 0.1 -
9397 750 13139
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 01 -- 10 May 2004
5 of 16
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