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Part: 74LVCH32373A
Category:
Logic
-> Latches
Description: 74LVCH32373A; 32-bit Transparent D-type Latch With 5 V Tolerant Inputs/outputs; 3-state;; Package: SOT536-1 (LFBGA96)
Company: Philips Semiconductors
Datasheet: Download 74LVCH32373A datasheet File size : 143 kB
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INTEGRATED CIRCUITS
DATA SHEET
74LVCH32373A 32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-state
Product specification File under Integrated Circuits, IC24 1999 Nov 24
Philips Semiconductors
Product specification
32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-state
FEATURES · 5 V tolerant inputs/outputs for interfacing with 5 V logic · Wide supply voltage range from 1.2 to 3.6 V · CMOS low power consumption · MULTIBYTETM flow-trough standard pin-out architecture · Low inductance multiple power and ground pins for minimum noise and ground bounce · Direct interface with TTL levels · Bus hold on data inputs · Typical output ground bounce voltage: VOLP 2 V at VCC = 3.3 V and Tamb = 25 °C · Power off disables outputs, permitting live insertion · Packaged in plastic fine-pitch ball grid array package. DESCRIPTION The 74LVCH32373A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices in a mixed 3.3 or 5 V environment. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf 2.5 ns. SYMBOL tPHL/tPLH PARAMETER propagation delay nDn to nQn nLE to nQn CI CPD Note 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; (CL × VCC2 × fo) = sum of the outputs. input capacitance power dissipation capacitance per buffer VI = GND to VCC; note 1 CL = 50 pF; VCC = 3.3 V CL = 50 pF; VCC = 3.3 V 3.0 3.4 5.0 26 CONDITIONS
74LVCH32373A
The 74LVCH32373A is a 32-bit transparent D-type latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. One latch enable (nLE) input and one output enable (nOE) are provided for each octal. Inputs can be driven from either 3.3 or 5 V devices. The 74LVCH32373A consists of 4 sections of eight D-type transparent latches with 3-state true outputs. When input nLE is HIGH, data at the nDn inputs enter the latches. In this condition the latches are transparent, i.e. a latch output will change each time its corresponding D-input changes. When input nLE is LOW the latches store the information that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of nLE. When input nOE is LOW, the contents of the eight latches are available at the outputs. When input nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches. The 74LVCH32373A bus hold data input circuits eliminate the need for external pull-up resistors to hold unused inputs.
TYPICAL ns ns pF pF
UNIT
1999 Nov 24
2
Philips Semiconductors
Product specification
32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-state
FUNCTION TABLE See note 1. INPUTS OPERATING MODE nOE Enable and read register (transparent mode) Latch and read register Latch register and disable outputs Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; Z = high-impedance OFF-state. ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE 74LVCH32373AEC PINNING SYMBOL nDn nLE nQn GND nOE VCC data inputs latch enable inputs (active HIGH) data outputs ground (0 V) output enable inputs (active LOW) DC supply voltage DESCRIPTION -40 to +85 °C PINS 96 PACKAGE LFBGA96 L L L L H H nLE H H L L L L nDn L H l h l h
74LVCH32373A
INTERNAL LATCHES L H L H L H
OUTPUTS nQn L H L H Z Z
MATERIAL plastic
CODE SOT536-1
1999 Nov 24
3
Philips Semiconductors
Product specification
32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-state
74LVCH32373A
handbook, full pagewidth
MNA492
6 5 4 3 2 1
1D1 1D3 1D5 1D7 2D1 2D3 2D5 2D7 3D1 3D3 3D5 3D7 4D1 4D3 4D5 4D6 1D0 1D2 1D4 1D6 2D0 2D2 2D4 2D6 3D0 3D2 3D4 3D6 4D0 4D2 4D4 4D7 1LE GND VCC GND GND VCC GND 2LE 3LE GND VCC GND GND VCC GND 4LE
1OE GND VCC GND GND VCC GND 2OE 3OE GND VCC GND GND VCC GND 4OE 1Q0 1Q2 1Q4 1Q6 2Q0 2Q2 2Q4 2Q6 3Q0 3Q2 3Q4 3Q6 4Q0 4Q2 4Q4 4Q7 1Q1 1Q3 1Q5 1Q7 2Q1 2Q3 2Q5 2Q7 3Q1 3Q3 3Q5 3Q7 4Q1 4Q3 4Q5 4Q6 A B C D E F G H J K L M N P R T
Fig.1 Pin configuration.
handbook, full pagewidth
1D0
D
Q
1Q0
2D0
D
Q
2Q0
LATCH 1
LATCH 9
LE
LE
LE
LE
1LE 1OE to 7 other channels
2LE 2OE to 7 other channels
3D0
D
Q
3Q0
4D0
D
Q
4Q0
LATCH 17
LATCH 25
LE
LE
LE
LE
3LE 3OE to 7 other channels
4LE 4OE to 7 other channels
MNA493
Fig.2 Logic symbol.
1999 Nov 24
4
Philips Semiconductors
Product specification
32-bit transparent D-type latch with 5 V tolerant inputs/outputs; 3-state
74LVCH32373A
handbook, halfpage
VCC
data input
to internal circuit
MNA473
Fig.3 Bus hold circuit.
1999 Nov 24
5
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