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Details, datasheet, quote on part number:74LVT16373A
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| Part: | 74LVT16373A |
| Category: | Logic => Latches |
| Description: | 74LVT16373A; 3.3V LVT 16-bit Transparent D-type Latch (3-State);; Package: SOT362-1 (TSSOP48), SOT370-1 (SSOP48) |
| Company: | Philips Semiconductors |
| Datasheet: | Download 74LVT16373A datasheet File size : 99 kB |
| Request For quote: | Find where to buy 74LVT16373A
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Datasheet text preview:
INTEGRATED CIRCUITS
74LVT16373A 3.3V LVT 16-bit transparent D-type latch (3-State)
Product specification Supersedes data of 1994 Dec 15 IC23 Data Handbook 1998 Feb 19
Philips Semiconductors
Philips Semiconductors
Product specification
3.3V 16-bit transparent D-type latch (3-State)
74LVT16373A
FEATURES
· 16-bit transparent latch · 3-State buffers · Output capability: +64mA/-32mA · TTL input and output switching levels · Input and output interface capability to systems at 5V supply · Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
DESCRIPTION
The 74LVT16373A is a high-performance BiCMOS product designed for VCC operation at 3.3V. This device is a 16-bit transparent D-type latch with non-inverting 3-State bus compatible outputs. The device can be used as two 8-bit latches or one 16-bit latch. When enable (E) input is High, the Q outputs follow the data (D) inputs. When enable is taken Low, the Q outputs are latched at the levels of the D inputs one setup time prior to the High-to-Low transition.
· Live insertion/extraction permitted · Power-up reset · Power-up 3-State · No bus current loading when output is tied to 5V bus · Latch-up protection exceeds 500mA per JEDEC Std 17 · ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN COUT ICCZ PARAMETER Propagation delay nDx to nQx Input capacitance Output capacitance Total supply current CL = 50pF; VCC = 3.3V VI = 0V or 3.0V Outputs disabled; VO = 0V or 3.0V Outputs disabled; VCC = 3.6V CONDITIONS Tamb = 25°C TYPICAL 1.9 3 9 70 UNIT ns pF pF µA
ORDERING INFORMATION
PACKAGES 48-Pin Plastic SSOP Type III 48-Pin Plastic TSSOP Type II TEMPERATURE RANGE 40°C to +85°C 40°C to +85°C OUTSIDE NORTH AMERICA 74LVT16373A DL 74LVT16373A DGG NORTH AMERICA VT16373A DL VT16373A DGG DWG NUMBER SOT370-1 SOT362-1
LOGIC SYMBOL
47 46 44 43 41 40 38 37
PIN DESCRIPTION
PIN NUMBER 47, 46, 44, 43, 41, 40, 38, 37, 36, 35, 33, 32, 30, 29, 27, 26 SYMBOL 1D0 1D7 2D0 2D7 1Q0 1Q7 2Q0 2Q7 1OE, 2OE FUNCTION Data inputs Data outputs Output enable inputs (active-Low) Enable inputs (active-High) Ground (0V) Positive supply voltage
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 48 1 1LE 1OE 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7
2, 3, 5, 6, 8, 9, 11, 12, 13, 14, 16, 17, 19, 20, 22, 23 1, 24
2 36
3 35
5 33
6 32
8 30
9 29
11 27
12 26
48, 25 4, 10, 15, 21, 28, 34, 39, 45 7, 18, 31, 42
1E, 2E GND VCC
2D0 2D21 2D2 2D3 2D4 2D5 2D6 2D7 25 24 2LE 2OE 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
13
14
16
17
19
20
22
23
SA00044
1998 Feb 19
2
853-1780 18989
Philips Semiconductors
Product specification
3.3V 16-bit transparent D-type latch (3-State)
74LVT16373A
LOGIC SYMBOL (IEEE/IEC)
1OE 1LE 2OE 2LE 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 1 48 24 25 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 4D 2 1EN C3 2EN C4 1 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23
PIN CONFIGURATION
1OE 1Q0 1Q1 GND 1Q2 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 GND 1Q6 1Q7 2Q0 2Q1 GND 2Q2 2Q3 V CC 2Q4 2Q5 GND 2Q6 2Q7 2OE 1Q3 V CC 1Q4 1Q5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1D3 V CC 1D4 1D5 GND 1D6 1D7 2D0 2D1 GND 2D2 2D3 V CC 2D4 2D5 GND 2D6 2D7 2LE 1 2 3 4 5 48 47 46 45 44 1LE 1D0 1D1 GND 1D2
3D
SW00010
SA00043
LOGIC DIAGRAM
nD0 nD1 nD2 nD3 nD4 nD5 nD6 nD7
D
D
D
D
D
D
D
D
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
nLE
nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7
SA00046
1998 Feb 19
3
Philips Semiconductors
Product specification
3.3V 16-bit transparent D-type latch (3-State)
74LVT16373A
FUNCTION TABLE
INPUTS nOE L L L L L H H H= h= L= l= NC = X= Z= = nE H H L L H nDx L H l h X X nDx INTERNAL REGISTER L H L H NC NC nDx OUTPUTS OPERATING MODE MODE nQ0 nQ7 L H L H NC Z Z Enable and read register Latch and read register Hold Disable outputs
High voltage level High voltage level one set-up time prior to the High-to-Low E transition Low voltage level Low voltage level one set-up time prior to the High-to-Low E transition No change Don't care High impedance "off " state High-to-Low E transition
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VOUT IOUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 VO < 0 Output in Off or High state Output in Low state DC output current output current Output in High state Storage temperature range 64 65 to +150 °C VI < 0 CONDITIONS RATING 0.5 to +4.6 50 0.5 to +7.0 50 0.5 to +7.0 128 mA UNIT V mA V mA V
DC output diode current DC output voltage3
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Input voltage High-level output current Low-level output current Low-level output current; current duty cycle 50%; f 1kHz Input transition rise or fall rate; Outputs enabled Operating free-air temperature range 40 PARAMETER LIMITS MIN 2.7 0 2.0 0.8 32 32 64 10 +85 ns/V °C MAX 3.6 5.5 UNIT V V V V mA mA
1998 Feb 19
4
Philips Semiconductors
Product specification
3.3V 16-bit transparent D-type latch (3-State)
74LVT16373A
DC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL VIK VOH PARAMETER Input clamp voltage High-level output voltage TEST CONDITIONS VCC = 2.7V; IIK = 18mA VCC = 2.7 to 3.6V; IOH = 100µA VCC = 2.7V; IOH = 8mA VCC = 3.0V; IOH = 32mA VCC = 2.7V; IOL = 100µA VCC = 2.7V; IOL = 24mA VOL Lowlevel output voltage VCC = 3.0V; IOL = 16mA VCC = 3.0V; IOL = 32mA VCC = 3.0V; IOL = 64mA VRST Power-up output Low voltage5 VCC = 3.6V; IO = 1mA; VI = GND or VCC VCC = 3.6V; VI = VCC or GND II Input leakage current leakage current VCC = 0 or 3.6V; VI = 5.5V VCC = 3.6V; VI = VCC VCC = 3.6V; VI = 0 IOFF IHOLD Output off current Bus Hold current D inputs7 Current into an output in the High state when VO > VCC Power up/down 3-State output current3 3-State output High current 3-State output Low current Quiescent supply current Additional supply current per input pin2 VCC = 0V; VI or VO = 0 to 4.5V VCC = 3V; VI = 0.8V VCC = 3V; VI = 2.0V VCC = 0V to 3.6V; VCC = 3.6V IEX IPU/PD IOZH IOZL ICCH ICCL ICCZ ICC VO = 5.5V; VCC = 3.0V VCC 1.2V; VO = 0.5V to VCC; VI = GND or VCC; OE/OE = Don't care VCC = 3.6V; VO = 3.0V; VI = VIH or VIL VCC = 3.6V; VO = 0.5V; VI = VIH or VIL VCC = 3.6V; Outputs High, VI = GND or VCC, IO = 0 VCC = 3.6V; Outputs Low, VI = GND or VCC, IO = 0 VCC = 3.6V; Outputs Disabled; VI = GND or VCC, IO = 06 VCC = 3V to 3.6V; One input at VCC-0.6V, Other inputs at VCC or GND 75 75 ±500 50 1 0.5 0.5 0.07 4.0 0.07 0.1 125 ±100 5 5 0.12 6 0.12 0.2 mA mA µA µA µA Data pins4 ins Control pins VCC-0.2 2.4 2.0 Temp = -40°C to +85°C MIN TYP1 .85 VCC 2.5 2.3 0.07 0.3 0.25 0.3 0.4 0.1 0.1 0.4 0.1 -0.4 0.1 135 -135 µA 0.2 0.5 0.4 0.5 0.55 0.55 ±1 10 1 -5 ±100 µA µA V V V MAX 1.2 V UNIT
NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND. 3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 3.3V ± 0.3V a transition time of 100µsec is permitted. This parameter is valid for Tamb = 25°C only. 4. Unused pins at VCC or GND. 5. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. 6. ICCZ is measured with outputs pulled to VCC or GND. 7. This is the bus hold overdrive current required to force the input to the opposite logic state.
1998 Feb 19
5
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