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Part: 7AHCT373PWDH
Category:
Logic
-> Buffers/Inverters
-> 3-State
Description: Octal D-type Transparent Latch; 3-state
Company: Philips Semiconductors
Datasheet: Download 7AHCT373PWDH datasheet File size : 137 kB
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INTEGRATED CIRCUITS
DATA SHEET
74AHC373; 74AHCT373 Octal D-type transparent latch; 3-state
Product specification Supersedes data of 1998 Dec 11 File under Integrated Circuits, IC06 1999 Nov 23
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
FEATURES · ESD protection: HBM EIA/JESD22-A114-A exceeds 2 000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1 000 V · Balanced propagation delays · All inputs have Schmitt-trigger actions · Inputs accepts voltages higher than VCC · Common 3-state output enable input · Functionally identical to the `533', `563' and `573' · For AHC only: operates with CMOS input levels · For AHCT only: operates with TTL input levels · Specified from -40 to +85 °C and -40 to +125 °C. DESCRIPTION The 74AHC/AHCT373 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA Ground = 0 V; Tamb = 25 °C; tr = tf 3.0 ns.
74AHC373; 74AHCT373
The 74AHC/AHCT373 are octal D-type transparent latches featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A Latch Enable (LE) input and an Output Enable (OE) input are common to all latches. The `373' consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. The `373' is functionally identical to the `533', `563' and `573', but the `533' and `563' have inverted outputs and the `563' and `573' have a different pin arrangement.
TYPICAL SYMBOL tPHL/tPLH CI CO CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. PARAMETER propagation delay Dn to Qn; LE to Qn input capacitance output capacitance power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 CONDITIONS AHC CL = 15 pF; VCC = 5 V VI = VCC or GND 4.3 3.0 4.0 10 4.3 3.0 4.0 12 AHCT ns pF pF pF UNIT
1999 Nov 23
2
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
FUNCTION TABLE See note 1. INPUTS OPERATING MODES OE Enable and read register (transparent mode) Latch and read register Latch register and disable outputs Note 1. H = HIGH voltage level; L L L L H H LE H H L L X X Dn L H I h X X
74AHC373; 74AHCT373
INTERNAL LATCHES L H L H X X
OUTPUTS Q0 to Q7 L H L H Z Z
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; X = don't care; Z = high-impedance OFF-state. ORDERING INFORMATION OUTSIDE NORTH AMERICA 74AHC373D 74AHC373PW 74AHCT373D 74AHCT373PW PINNING PIN 1 2, 5, 6, 9, 12, 15, 16 and 19 3, 4, 7, 8, 13, 14, 17 and 18 10 11 20 OE Q0 to Q7 D0 to D7 GND LE VCC SYMBOL latch outputs data inputs ground (0 V) latch enable input (active HIGH) DC supply voltage DESCRIPTION output enable input (active LOW) PACKAGES NORTH AMERICA PINS 74AHC373D 74AHC373PW DH 74AHCT373D 7AHCT373PW DH 20 20 20 20 PACKAGE SO TSSOP SO TSSOP MATERIAL plastic plastic plastic plastic CODE SOT163-1 SOT360-1 SOT163-1 SOT360-1
1999 Nov 23
3
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
handbook, halfpage
OE 1 Q0 2 D0 3 D1 4 Q1 5
20 VCC 19 Q7 18 D7 17 D6 16 Q6
handbook, halfpage
11 3 4 7 8 13 14 17 18 LE D0 D1 D2 D3 D4 D5 D6 D7 OE 1 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19
373
Q2 6 D2 7 D3 8 Q3 9 GND 10
MNA185
15 Q5 14 D5 13 D4 12 Q4 11 LE
MNA186
Fig.1 Pin configuration.
Fig.2 Logic symbol.
handbook, halfpage
1 11
EN C1 2 5 6 9 12 15 16 19
MNA187
3 4 7 8 13 14 17 18
1D
Fig.3 IEC logic symbol.
1999 Nov 23
4
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
handbook, halfpage
3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7 LATCH 1 to 8 3-STATE OUTPUTS
Q0 Q1 Q2 Q3
2 5 6 9
handbook, halfpage
LE
Q4 12 Q5 15 Q6 16 Q7 19 D Q LE
MNA189
LE LE
11 LE 1 OE
MNA184
Fig.4 Functional diagram.
Fig.5 Logic diagram (one latch).
D0
D1
D2
D3
D4
D5
D6
D7
handbook, full pagewidth
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH 1 LE LE
LATCH 2 LE LE
LATCH 3 LE LE
LATCH 4 LE LE
LATCH 5 LE LE
LATCH 6 LE LE
LATCH 7 LE LE
LATCH 8 LE LE
LE OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
MNA199
Fig.6 Logic diagram.
1999 Nov 23
5
Others parts begin by 7a
7A-1
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