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Part: 7AHCT573PWDH
Category:
Logic
-> Buffers/Inverters
-> 3-State
Description: Octal D-type Transparent Latch; 3-state
Company: Philips Semiconductors
Datasheet: Download 7AHCT573PWDH datasheet File size : 137 kB
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INTEGRATED CIRCUITS
DATA SHEET
74AHC573; 74AHCT573 Octal D-type transparent latch; 3-state
Product specification File under Integrated Circuits, IC06 1999 Sep 27
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
FEATURES · ESD protection: HBM EIA/JESD22-A114-A exceeds 2 000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1 000 V · Balanced propagation delays · All inputs have Schmitt-trigger actions · Common 3-state output enable input · Functionally identical to the `563' and `373' · Inputs accepts voltages higher than VCC · For AHC only: operates with CMOS input levels · For AHCT only: operates with TTL input levels · Specified from -40 to +85 and +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf 3.0 ns. DESCRIPTION
74AHC573; 74AHCT573
The 74AHC/AHCT573 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT573 are octal D-type transparent latches featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A Latch Enable (LE) input and an Output Enable (OE) input are common to all latches. The `573' consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. The `573' is functionally identical to the `533', `563' and `373', but the `533' and `563' have inverted outputs and the `563' and `373' have a different pin arrangement.
TYPICAL SYMBOL tPHL/tPLH CI CO CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. PARAMETER propagation delay Dn to Qn; LE to Qn input capacitance output capacitance power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 CONDITIONS AHC CL = 15 pF; VCC = 5 V VI = VCC or GND 4.2 3.0 4.0 12 3.9 3.0 4.0 18 AHCT ns pF pF pF UNIT
1999 Sep 27
2
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
FUNCTION TABLE See note 1. INPUTS OPERATING MODES OE Enable and read register (transparent mode) Latch and read register Latch register and disable outputs Note 1. H = HIGH voltage level; L L L L H H LE H H L L L L Dn L H I h l h
74AHC573; 74AHCT573
INTERNAL LATCHES L H L H L H
OUTPUTS Q0 to Q7 L H L H Z Z
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; Z = high-impedance OFF-state. ORDERING INFORMATION OUTSIDE NORTH AMERICA 74AHC573D 74AHC573PW 74AHCT573D 74AHCT573PW PINNING PIN 1 2 to 9 10 11 12 to 19 20 OE D0 to D7 GND LE Q7 to Q0 VCC SYMBOL data inputs ground (0 V) latch enable input (active HIGH) 3-state latch outputs DC supply voltage DESCRIPTION 3-state output enable input (active LOW) PACKAGES NORTH AMERICA PINS 74AHC573D 74AHC573PW DH 74AHCT573D 7AHCT573PW DH 20 20 20 20 PACKAGE SO TSSOP SO TSSOP MATERIAL plastic plastic plastic plastic CODE SOT163-1 SOT360-1 SOT163-1 SOT360-1
1999 Sep 27
3
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC573; 74AHCT573
handbook, halfpage
OE 1 D0 2 D1 3 D2 4 D3 5
20 VCC 19 Q0 18 Q1 17 Q2 16 Q3
handbook, halfpage
11 2 3 4 5 6 7 8 9 LE D0 D1 D2 D3 D4 D5 D6 D7 OE 1 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12
573
D4 6 D5 7 D6 8 D7 9 GND 10
MNA388
15 Q4 14 Q5 13 Q6 12 Q7 11 LE
MNA389
Fig.1 Pin configuration.
Fig.2 Logic symbol.
handbook, halfpage
11 1
C1 EN
handbook, halfpage
2 3 19 18 17 16 15 14 13 12
MNA390
D0 D1 D2 D3 D4 D5 D6 D7 LATCH 1 to 8 3-STATE OUTPUTS
Q0 19 Q1 18 Q2 17 Q3 16 Q4 15 Q5 14 Q6 13 Q7 12
2 3 4 5 6 7 8 9
1D
4 5 6 7 8 9
11 LE 1 OE
MNA391
Fig.3 IEC logic symbol.
Fig.4 Functional diagram.
1999 Sep 27
4
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74AHC573; 74AHCT573
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH 1 LE LE OE
LATCH 2 LE
LATCH 3 LE
LATCH 4 LE
LATCH 5 LE
LATCH 6 LE
LATCH 7 LE
LATCH 8 LE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
MNA392
Fig.5 Logic diagram.
RECOMMENDED OPERATING CONDITIONS 74AHC SYMBOL VCC VI VO Tamb tr,tf (t/f) PARAMETER DC supply voltage input voltage output voltage operating ambient temperature range input rise and fall rates CONDITIONS MIN. 2.0 0 0 see DC and AC -40 characteristics per device -40 VCC = 3.3 V ±0.3 V VCC = 5 V ±0.5 V - - TYP. MAX. MIN. 5.0 - - +25 +25 - - 5.5 5.5 VCC +85 100 20 4.5 0 0 -40 - - TYP. MAX. 5.0 - - +25 +25 - - 5.5 5.5 VCC +85 - 20 V V V °C ns/V 74AHCT UNIT
+125 -40
+125 °C
1999 Sep 27
5
Others parts begin by 7a
7A-1
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