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Part: 7LVC240APWDH
Category:
Logic
-> Buffers/Inverters
-> 3-State
Description: Octal Buffer/line Driver With 5-volt Tolerant Inputs/outputs; Inverting 3-state
Company: Philips Semiconductors
Datasheet: Download 7LVC240APWDH datasheet File size : 0 kB
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INTEGRATED CIRCUITS
74LVC240A Octal buffer/line driver with 5-volt tolerant inputs/outputs; inverting (3-State)
Product specification IC24 Data Handbook 1998 May 20
Philips Semiconductors
Philips Semiconductors
Product specification
Octal buffer/line driver with 5-volt tolerant inputs/outputs; inverting (3-State)
74LVC240A
FEATURES
· 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic · Supply voltage range of 1.2V to 3.6V · Complies with JEDEC standard no. 8-1A · CMOS low power consumption · Direct interface with TTL levels · High impedance when VCC = 0V
DESCRIPTION
The 74LVC240A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. These features allow the use of these devices as translators in a mixed 3.3V/5V environment. The `240A is an octal non-inverting buffer/line driver with 3-State outputs. The 3-State outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on nOE causes the outputs to assume a high impedance OFF-state. Schmitt-trigger action at all inputs makes the circuit highly tolerant for slower input rise and fall times. The '240' is functionally identical to the '244', but the '244' has inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf v2.5 ns SYMBOL tPHL/tPLH CI CP D PARAMETER Propagation delay 1An to 1Yn; 2An to 2Yn Input capacitance Power dissipation capacitance per buffer Notes 1 and 2 CONDITIONS CL = 50pF VCC = 3.3V TYPICAL 3.5 5.0 20 UNIT ns pF pF
NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD x VCC2 x fi + S (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL x VCC2 x fo) = sum of outputs. 2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES 20-Pin Plastic Small Outline (SO) 20-Pin Plastic Shrink Small Outline (SSOP) Type II 20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I TEMPERATURE RANGE 40°C to +85°C 40°C to +85°C 40°C to +85°C OUTSIDE NORTH AMERICA 74LVC240A D 74LVC240A DB 74LVC240A PW NORTH AMERICA 74LVC240A D 74LVC240A DB 7LVC240APW DH PKG. DWG. # SOT163-1 SOT339-1 SOT360-1
1998 May 20
2
853-1981 19419
Philips Semiconductors
Product specification
Octal buffer/line driver with 5-volt tolerant inputs/outputs; inverting (3-State)
74LVC240A
PIN DESCRIPTION
PIN NUMBER 1 2, 4, 6, 8 3, 5, 7, 9 10 17, 15, 13, 11 18, 16, 14, 12 19 20 SYMBOL 1OE 1A0 to 1A3 2Y0 to 2Y3 GND 2A0 to 2A3 1Y0 to 1Y3 2OE VCC FUNCTION Output enable input (active LOW) Data inputs Bus outputs Ground (0V) Bus inputs Bus outputs Output enable input (active-LOW) Positive power supply
FUNCTION TABLE
INPUTS nOE L L H H L X Z nAn L H X OUTPUT nYn H L Z
= HIGH voltage level = LOW voltage level = Don't care = High impedance OFF-state
LOGIC SYMBOL PIN CONFIGURATION
2 1A 0 17 2A 0 4 1A 1 15 2A 1 1OE 1A0 2Y0 1A1 2Y1 1A2 2Y2 1A3 2Y3 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 V CC 2OE 1Y0 2A0 1Y1 2A1 1Y2 2A2 1Y3 2A3 2 1A 0 1A 1 1A 2 1A 3 1OE 2Y 0 3 2Y 1 5 2Y 2 7 2Y 3 9 1Y 0 18 1Y 1 16 1Y 2 14 1Y 3 12 6 1A 2 13 2A 2 8 1A 3 11 2A 3 1 1OE 19 2OE 1Y 0 18 2Y 0 3 1Y 1 16 2Y 1 5 1Y 2 14 2Y 2 7 1Y 3 12 2Y 3 9
SV00608
FUNCTIONAL DIAGRAM
GND 10
SV00212
4 6
LOGIC SYMBOL (IEEE/IEC)
1 EN 18 16 14 12
8 1
2 4 6 8
17 2A 0 15 2A 1 13 2A 2 11 2A 3
19
EN 19 2OE 9 7 5 3
11 13 15 17
SV00610
SV00611
1998 May 20
3
Philips Semiconductors
Product specification
Octal buffer/line driver with 5-volt tolerant inputs/outputs; inverting (3-State)
74LVC240A
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VCC VI VO Tamb tr, tf PARAMETER DC supply voltage (for max. speed performance) DC supply voltage (for low-voltage applications) DC Input voltage range DC Output voltage range; output HIGH or LOW state DC output voltage range; output 3-State Operating ambient temperature range in free-air Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V CONDITIONS MIN 2.7 1.2 0 0 0 40 0 0 MAX 3.6 3.6 5.5 VCC 5.5 +85 20 10 °C ns/V V V V V UNIT
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC IIK VI IOK VO IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC input voltage DC output diode current DC output voltage; output HIGH or LOW state DC output voltage; output 3-State DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package plastic mini-pack (SO) plastic shrink mini-pack (SSOP and TSSOP) above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K VI t0 Note 2 VO uVCC or VO t 0 Note 2 Note 2 VO = 0 to VCC CONDITIONS RATING 0.5 to +6.5 50 0.5 to +6.5 "50 0.5 to VCC +0.5 0.5 to 6.5 "50 "100 65 to +150 500 500 UNIT V mA V mA V mA mA °C
mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 May 20
4
Philips Semiconductors
Product specification
Octal buffer/line driver with 5-volt tolerant inputs/outputs; inverting (3-State)
74LVC240A
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C MIN VIH HIGH level Input voltage level Input voltage VCC = 1.2V VCC = 2.7 to 3.6V LOW level Input voltage level Input voltage VCC = 1.2V VCC = 2.7 to 3.6V VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOH HIGH level output voltage level output voltage VCC = 3.0V; VI = VIH or VIL; IO = 100µA VCC = 3.0V; VI = VIH or VIL; IO = 18mA VCC = 3.0V; VI = VIH or VIL; IO = 24mA VCC = 2.7V; VI = VIH or VIL; IO = 12mA VOL LOW level output voltage VCC = 3.0V; VI = VIH or VIL; IO = 100µA VCC = 3.0V; VI = VIH or VIL; IO = 24mA II IOZ Ioff ICC ICC Input leakage leakage current2 current VCC = 3 6V; VI = 5 5V or GND 3.6V; 5.5V or GND VCC = 3.6V; VI = VIH or VIL; VO = 5.5V or GND VCC = 0.0V; VI or VO = 5.5V VCC = 3.6V; VI = VCC or GND; IO = 0 VCC = 2.7V to 3.6V; VI = VCC 0.6V; IO = 0 "0.1 0.1 0.1 0.1 5 GND VCC*0.5 VCC*0.2 VCC*0.6 VCC*0.8 0.40 0.20 0.55 "5 "10 "10 10 500 µA µA µA µA µA V VCC V VCC 2.0 GND V 0.8 TYP1 MAX V UNIT
VIL
3-State output OFF-state current Power off leakage current Quiescent supply current Additional quiescent supply current per input pin
NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 2. The specified overdrive current at the data input forces the data input to the opposite logic input state.
AC CHARACTERISTICS
GND = 0V; tr = tf v 2.5ns; CL = 50pF; RL = 500; Tamb = 40°C to +85°C. LIMITS SYMBOL PARAMETER Propagation delay 1An to 1Yn; 2An to 2Yn 3-State output enable time 1OE to 1Yn; 2OE to 2Yn 3-State output disable time 1OE to 1Yn; 2OE to 2Yn WAVEFORM VCC = 3.3V ±0.3V MIN tPLH tPHL tPZH tPZL tPHZ tPLZ 1, 3 1.5 TYP1 3.5 MAX 6.5 VCC = 2.7V MIN 1.5 MAX 7.5 VCC = 1.2V TYP 16.0 ns UNIT
2, 3
1.5
4.3
8.0
1.5
9.0
19.0
ns
2, 3
1.5
3.7
7.0
1.5
8.0
17.0
ns
NOTE: 1. Unless otherwise stated, all typical values are at VCC = 3.3V and Tamb = 25°C.
1998 May 20
5
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7L-1
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