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Part: 7LVC573APWDH
Category:
Logic
-> Buffers/Inverters
-> 3-State
Description: Octal D-type Transparent Latch With 5-volt Tolerant Inputs/outputs 3-state
Company: Philips Semiconductors
Datasheet: Download 7LVC573APWDH datasheet File size : 0 kB
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INTEGRATED CIRCUITS
74LVC573A Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State)
Product specification 1998 Jul 29
Philips Semiconductors
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State)
74LVC573A
FEATURES
· 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic · Supply voltage range of 2.7V to 3.6V · Complies with JEDEC standard no. 8-1A · Inputs accept voltages up to 5.5V · CMOS low power consumption · Direct interface with TTL levels · High impedance when VCC = 0V · Flow-through pin-out architecture
DESCRIPTION
The 74LVC573A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment.
The 74LVC573A is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus-oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all internal latches. The '573A' consists of eight D-type transparent latches with 3-State true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches are transparent, i.e. a latch output will change each time its corresponding D-input changes. When LE is LOW, the latches store the information that was present at the D-inputs one setup time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches. The '573A' is functionally identical to the '373A', but the '373A' has a different pin arrangement.
QUICK REFERENCE DATA
SYMBOL tPHL/tPLH CI CP D PARAMETER Propagation delay Dn to Qn; LE to Qn Input capacitance Power dissipation capacitance per latch Notes 1 and 2 CONDITIONS CL = 50pF VCC = 3.3V TYPICAL UNIT ns pF pF
4.3 4.6 5.0 20
NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD x VCC2 x fi + S (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL x VCC2 x fo) = sum of outputs. 2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES 20-Pin Plastic Shrink Small Outline (SO) 20-Pin Plastic Shrink Small Outline (SSOP) Type II 20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I TEMPERATURE RANGE 40°C to +85°C 40°C to +85°C 40°C to +85°C OUTSIDE NORTH AMERICA 74LVC573A D 74LVC573A DB 74LVC573A PW NORTH AMERICA 74LVC573A D 74LVC573A DB 7LVC573APW DH PKG. DWG. # SOT163-1 SOT339-1 SOT360-1
1998 Jul 29
2
853-1862 19804
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State)
74LVC573A
PIN DESCRIPTION
PIN NUMBER 1 2, 3, 4, 5, 6, 7, 8, 9 19, 18, 17, 16, 15, 14, 13, 12 10 11 20 SYMBOL OE D0-D7 Q0-Q7 GND LE VCC FUNCTION Output enable input (active-Low) Data inputs Data outputs Ground (0V) Latch enable input (active-High) Positive supply voltage
LOGIC SYMBOL (IEEE/IEC)
11 1
C1 EN1
2 3 4 5 6
1D
19 18 17 16 15 14 13 12
PIN CONFIGURATION
7 8 9
OE D0 D1 D2 D3 D4 D5 D6 D7
1 2 3 4 5 6 7 8 9
20 VCC 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7 11 LE 2 3 4 5 6 7 8 9 11 D0 D1 D2 D3 D4 D5 D6 D7 LE OE LATCH 1 to 8
SA00397
FUNCTIONAL DIAGRAM
Q0 Q1 Q2 Q3 3-State OUTPUTS Q4 Q5 Q6 Q7
19 18 17 16 15 14 13 12
GND 10
SA00395
LOGIC SYMBOL
1
1
SA00398
2 3 4 5 6 7 8 9
D0 D1 D2 D3 D4 D5 D6 D7
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6
19 18 17 16 15 14 13 12
LE
Q7
11
SA00396
1998 Jul 29
3
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State)
74LVC573A
LOGIC DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH 1 LE LE
LATCH 2 LE LE
LATCH 3 LE LE
LATCH 4 LE LE
LATCH 5 LE LE
LATCH 6 LE LE
LATCH 7 LE LE
LATCH 8 LE LE
LE OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
SA00399
FUNCTION TABLE
INPUTS
OPERATING MODES MODES
OUTPUTS Dn L H l h l h INTERNAL LATCHES LATCHES L H L H L H Q0 to Q7 L H L H Z Z
OE Enable and read register (transparent mode) Latch and read register Latch register and disable outputs H h L l X Z L L L L H H
LE H H L L L L
= HIGH voltage level = HIGH voltage level one setup time prior to the HIGH-to-LOW LE transition = LOW voltage level = LOW voltage level one setup time prior to the HIGH-to-LOW LE transition = Don't care = High impedance OFF-state
1998 Jul 29
4
Philips Semiconductors
Product specification
Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State)
74LVC573A
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL PARAMETER DC supply voltage (for max. speed performance) VCC VI VO Tamb tr, tf DC supply voltage (for low-voltage applications) DC Input voltage range DC output voltage range; output HIGH or LOW state DC output voltage range; output 3-State Operating ambient temperature range in free-air Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V CONDITIONS MIN 2.7 1.2 0 0 0 40 0 0 MAX 3.6 V 3.6 5.5 VCC 5.5 +85 20 10 °C ns/V V V UNIT
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC IIK VI IOK VO IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC input voltage DC output diode current DC output voltage; output HIGH or LOW state DC output voltage; output 3-State DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package plastic mini-pack (SO) plastic shrink mini-pack (SSOP and TSSOP) above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K VI t0 Note 2 VO uVCC or VO t 0 Note 2 Note 2 VO = 0 to VCC CONDITIONS RATING 0.5 to +6.5 50 0.5 to +6.5 "50 0.5 to VCC +0.5 0.5 to 6.5 "50 "100 65 to +150 500 500 UNIT V mA V mA V mA mA °C
mW
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Jul 29
5
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