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Details, datasheet, quote on part number:ADC0803-1LCN
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Datasheet text preview:
INTEGRATED CIRCUITS
ADC0803/0804 CMOS 8-bit A/D converters
Product data Supersedes data of 2001 Aug 03 2002 Oct 17
Philips Semiconductors
Philips Semiconductors
Product data
CMOS 8-bit A/D converters
ADC0803/0804
DESCRIPTION
The ADC0803 family is a series of three CMOS 8-bit successive approximation A/D converters using a resistive ladder and capacitive array together with an auto-zero comparator. These converters are designed to operate with microprocessor-controlled buses using a minimum of external circuitry. The 3-State output data lines can be connected directly to the data bus. The differential analog voltage input allows for increased common-mode rejection and provides a means to adjust the zero-scale offset. Additionally, the voltage reference input provides a means of encoding small analog voltages to the full 8 bits of resolution.
PIN CONFIGURATION
D, N PACKAGES CS 1 RD 2 WR 3 CLK IN 4 20 VCC 19 CLK R 18 D0 17 D1 16 D2 15 D3 14 D4 13 D5 12 D6 11 D7 TOP VIEW
INTR 5 VIN(+) 6 VIN() 7 A GND 8
FEATURES
VREF/2 9 D GND 10
· Compatible with most microprocessors · Differential inputs · 3-State outputs · Logic levels TTL and MOS compatible · Can be used with internal or external clock · Analog input range 0 V to VCC · Single 5 V supply · Guaranteed specification with 1 MHz clock
SL00016
Figure 1. Pin configuration
APPLICATIONS
· Transducer-to-microprocessor interface · Digital thermometer · Digitally-controlled thermostat · Microprocessor-based monitoring and control systems
ORDERING INFORMATION
DESCRIPTION 20-pin plastic small outline (SO) package 20-pin plastic small outline (SO) package 20-pin plastic dual in-line package (DIP) 20-pin plastic dual in-line package (DIP) TEMPERATURE RANGE 0 to 70 °C 40 to 85 °C 0 to 70 °C 40 to +85 °C ORDER CODE ADC0803CD, ADC0804CD ADC0803LCD, ADC0804LCD ADC0803CN, ADC0804CN ADC0803LCN, ADC0804LCN TOPSIDE MARKING ADC0803-1CD, ADC0804-1CD ADC0803-1LCD, ADC0804-1LCD ADC0803-1CN, ADC0804-1CN ADC0803-1LCN, ADC0804-1LCN DWG # SOT163-1 SOT163-1 SOT146-1 SOT146-1
ABSOLUTE MAXIMUM RATINGS
SYMBOL VCC Supply voltage Logic control input voltages All other input voltages Tamb Operating temperature range ADC0803LCD/ADC0804LCD ADC0803LCN/ADC0804LCN ADC0803CD/ADC0804CD ADC0803CN/ADC0804CN Storage temperature Lead soldering temperature (10 seconds) Maximum power N package D package dissipation1 Tamb = 25 °C (still air) 1690 1390 mW mW PARAMETER CONDITIONS RATING 6.5 0.3 to +16 0.3 to (VCC +0.3) 40 to +85 40 to +85 0 to +70 0 to +70 65 to +150 230 UNIT V V V °C °C °C °C °C °C
Tstg Tsld PD
NOTE: 1. Derate above 25 °C, at the following rates: N package at 13.5 mW/°C; D package at 11.1 mW/°C.
2002 Oct 17
2
Philips Semiconductors
Product data
CMOS 8-bit A/D converters
ADC0803/0804
BLOCK DIAGRAM
VIN (+) 6 VIN () 7
M
+
+
9
VREF/2 LADDER AND DECODER
8 A GND
AUTO ZERO COMPARATOR
V CC
20
D7 (MSB) (11) D6 D5 D4 D3 D2 D1 D0 (LSB) (12) (13) (14) (15) (16) (17) (18)
OUTPUT LATCHES SAR 10 D GND LE OE
3 WR 8BIT SHIFT REGISTER CLOCK
1 CS S INTR FF R 2 RD Q
5 INTR
4 CLK IN
19 CLK R
SL00017
Figure 2. Block diagram
2002 Oct 17
3
Philips Semiconductors
Product data
CMOS 8-bit A/D converters
ADC0803/0804
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0 V, fCLK = 1 MHz, Tmin Tamb Tmax, unless otherwise specified. LIMITS SYMBOL PARAMETER ADC0803 relative accuracy error (adjusted) ADC0804 relative accuracy error (unadjusted) RIN VREF/2 input resistance3 Analog input voltage range3 Over analog input voltage range VCC = 5V ±10%1 VCC = 5.25 VDC VCC = 4.75 VDC VIN = 5 VDC VIN = 0 VDC 1 0.005 0.005 2.0 DC common-mode error Power supply sensitivity Control inputs VIH VIL IIH IIL VT+ VT VH VOL VOH VOL Logical "1" input voltage Logical "0" input voltage Logical "1" input current Logical "0" input current 15 0.8 1 VDC VDC µADC µADC 3.5 2.1 2.0 0.4 2.4 VDC VDC VDC VDC VDC TEST CONDITIONS CONDITIONS Full-Scale adjusted VREF/2 = 2.500 VDC VCC = 0 V2 400 0.05 1/16 1/16 680 VCC+0.05 1/8 Min Typ Max 0.50 1 UNIT LSB LSB V LSB LSB
Clock in and clock R Clock in positive-going threshold voltage Clock in negative-going threshold voltage Clock in hysteresis (VT+)(VT) Logical "0" clock R output voltage Logical "1" clock R output voltage IOL = 360 µA, VCC = 4.75 VDC IOH = 360 µA, VCC = 4.75 VDC 2.7 1.5 0.6 3.1 1.8 1.3
Data output and INTR Logical "0" output voltage Data outputs INTR outputs VOH IOZL IOZH ISC ISC ICC Logical "1" output voltage "1" output voltage 3-State output leakage 3-State output leakage +Output short-circuit current Output short-circuit current Power supply current IOL = 1.6 mA, VCC = 4.75 VDC IOL = 1.0 mA, VCC = 4.75 VDC IOH = 360 µA, VCC = 4.75 VDC IOH = 10 µA, VCC = 4.75 VDC VOUT = 0 VDC, CS = logical "1" VOUT = 5 VDC, CS = logical "1" VOUT = 0 V, Tamb = 25 °C VOUT = VCC, Tamb = 25 °C fCLK = 1 MHz, VREF/2 = OPEN, CS = Logical "1", Tamb = 25 °C 4.5 9.0 12 30 3.0 3.5 2.4 4.5 3 3 VDC µADC µADC mADC mADC mA 0.4 0.4 VDC VDC
NOTES: 1. Analog inputs must remain within the range: 0.05 VIN VCC + 0.05 V. 2. See typical performance characteristics for input resistance at VCC = 5 V. 3. VREF/2 and VIN must be applied after the VCC has been turned on to prevent the possibility of latching.
2002 Oct 17
4
Philips Semiconductors
Product data
CMOS 8-bit A/D converters
ADC0803/0804
AC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER Conversion time fCLK Clock frequency1 Clock duty cycle1 CR tW(WR)L tACC t1H, t0H tW1, tR1 CIN Free-running conversion rate Start pulse width Access time 3-State control INTR delay Logic input=capacitance Output Output INTR RD RD WD or RD CS = 0, fCLK = 1 MHz INTR tied to WR CS = 0 CS = 0, CL = 100 pF CL = 10 pF, RL = 10 k See 3-State test circuit 30 75 70 100 5 5 100 100 150 7.5 7.5 TO FROM TEST CONDITIONS CONDITIONS fCLK = 1 MHz1 LIMITS Min 66 0.1 40 1.0 Typ Max 73 3.0 60 13690 UNIT µs MHz % conv/s ns ns ns ns pF pF
COUT 3-State output capacitance NOTE: 1. Accuracy is guaranteed at fCLK = 1 MHz. Accuracy may degrade at higher clock frequencies.
FUNCTIONAL DESCRIPTION
These devices operate on the Successive Approximation principle. Analog switches are closed sequentially by successive approximation logic until the input to the auto-zero comparator [ VIN(+)VIN() ] matches the voltage from the decoder. After all bits are tested and determined, the 8-bit binary code corresponding to the input voltage is transferred to an output latch. Conversion begins with the arrival of a pulse at the WR input if the CS input is low. On the High-to-Low transition of the signal at the WR or the CS input, the SAR is initialized, the shift register is reset, and the INTR output is set high. The A/D will remain in the reset state as long as the CS and WR inputs remain low. Conversion will start from one to eight clock periods after one or both of these inputs makes a Low-to-High transition. After the conversion is complete, the INTR pin will make a High-to-Low transition. This can be used to interrupt a processor, or otherwise signal the availability of a new conversion result. A read (RD) operation (with CS low) will clear the INTR line and enable the output latches. The device may be run in the free-running mode as described later. A conversion in progress can be interrupted by issuing another start command.
ANALOG OPERATION Analog Input Current
The analog comparisons are performed by a capacitive charge summing circuit. The input capacitor is switched between VIN(+)4 and VIN(), while reference capacitors are switched between taps on the reference voltage divider string. The net charge corresponds to the weighted difference between the input and the most recent total value set by the successive approximation register. The internal switching action causes displacement currents to flow at the analog inputs. The voltage on the on-chip capacitance is switched through the analog differential input voltage, resulting in proportional currents entering the VIN(+) input and leaving the VIN() input. These transient currents occur at the leading edge of the internal clock pulses. They decay rapidly so do not inherently cause errors as the on-chip comparator is strobed at the end of the clock period.
Input Bypass Capacitors and Source Resistance
Bypass capacitors at the input will average the charges mentioned above, causing a DC and an AC current to flow through the output resistance of the analog signal sources. This charge pumping action is worse for continuous conversions with the VIN(+) input at full scale. This current can be a few microamps, so bypass capacitors should NOT be used at the analog inputs of the VREF/2 input for high resistance sources (> 1 k). If input bypass capacitors are desired for noise filtering and a high source resistance is desired to minimize capacitor size, detrimental effects of the voltage drop across the input resistance can be eliminated by adjusting the full scale with both the input resistance and the input bypass capacitor in place. This is possible because the magnitude of the input current is a precise linear function of the differential voltage.
Digital Control Inputs
The digital control inputs (CS, WR, RD) are compatible with standard TTL logic voltage levels. The required signals at these inputs correspond to Chip Select, START Conversion, and Output Enable control signals, respectively. They are active-Low for easy interface to microprocessor and microcontroller control buses. For applications not using microprocessors, the CS input (Pin 1) can be grounded and the A/D START function is achieved by a negative-going pulse to the WR input (Pin 3). The Output Enable function is achieved by a logic low signal at the RD input (Pin 2), which may be grounded to constantly have the latest conversion present at the output.
2002 Oct 17
5
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