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Details, datasheet, quote on part number:ADC0820C
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| Part: | ADC0820C |
| Category: | Data Conversion => ADC (Analog to Digital Converters) => <10 bit |
| Description: | 8-bit, High-speed, Mp-compatible A/D Converter With Track/hold Function |
| Company: | Philips Semiconductors |
| Datasheet: | Download ADC0820C datasheet File size : 110 kB |
| Request For quote: | Find where to buy ADC0820C
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Datasheet text preview:
Philips Semiconductors Linear Products
Product specification
8-Bit, high-speed, µP-compatible A/D converter with track/hold function
ADC0820
DESCRIPTION
By using a half-flash conversion technique, the 8-bit ADC0820 CMOS A/D offers a 1.5µs conversion time while dissipating a maximum 75mW of power. The half-flash technique consists of 31 comparators, a most significant 4-bit ADC and a least significant 4-bit ADC. The input to the ADC0820 is tracked and held by the input sampling circuitry, eliminating the need for an external sample-and-hold for signals slewing at less than 100mV/µs. For ease of interface to microprocessors, the ADC0820 has been designed to appear as a memory location or I/O port without the need for external interfacing logic.
PIN CONFIGURATION
D, F, N Packages
V IN 1 20 19 18 17 16 15 14 13 12 11 TOP VIEW V DD NC OFL DB7 DB6 DB5 DB4 CS VREF(+) VREF()
DB0 2 DB1 3 DB2 4 DB3 5 WR/RDY MODE RD INT 6 7 8 9 10
FEATURES
GND
· Built-in track-and-hold function · No missing codes · No external clocking · Single supply--5VDC · Easy interface to all microprocessors, or operates stand-alone · Latched 3-State outputs · Logic inputs and outputs meet both MOS and TTL voltage level
specifications
APPLICATIONS
· Operates ratiometrically or with any reference value equal to or · 0V to 5V analog input voltage range with single 5V supply · No zero- or full-scale adjust required · Overflow output available for cascading · 0.3 standard width 20-pin DIP
ORDERING INFORMATION
DESCRIPTION 20-Pin Plastic Dual In-Line Package (DIP) 20-Pin Plastic Small Outline (SO) package less than VDD
· Microprocessor-based monitoring and control systems · Transducer/µP interface · Process control · Logic analyzers · Test and measurement
TEMPERATURE RANGE 0 to +70°C 0 to +70°C
ORDER CODE ADC0820CNEN ADC0820CNED
DWG # 0408B 1021B
August 31, 1994
568
853-1631 13721
Philips Semiconductors Linear Products
Product specification
8-Bit, high-speed, µP-compatible A/D converter with track/hold function
ADC0820
BLOCK DIAGRAM
VREF(+) OFL 4BIT FLASG ADC (4MSBs) OFL DB7 DB6 DB5 DB4
VREF() V IN VREF(+)
+
4BIT DAC
VREF() V RE F (+) 16
OUTPUT LATCH AND THREESTATE BUFFERS
4BIT FLASG ADC (4LSBs)
DB3 DB2 DB1 DB0
VREF() TIMING AND CONTROL CIRCUITRY
INT
MODE
WR/RDY
CS
RD
PIN DESCRIPTION
PIN NO 1 2 3 4 5 6 SYMBOL VIN DB0 DB1 DB2 DB3 WR/RDY Analog input; range=GNDVINVDD 3-state data output--Bit 0 (LSB) 3-state data output--Bit 1 3-state data output--Bit 2 3-state data output--Bit 3 DESCRIPTION
WR-RD Mode
WR: With CS Low, the conversion is started on the falling edge of WR. Approximately 800ns (the preset internal time out, tI) after the WR rising edge, the result of the conversion will be strobed into the output latch, provided that RD does not occur prior to this time out (see Figures 3a and 3b).
RD Mode
RDY: This is an open-drain output (no internal pull-up device). RDY will go Low after the falling edge of CS; RDY will go 3-State when the result of the conversion is strobed into the output latch. It is used to simplify the interface to a microprocessor system (see Figure 1). 7 Mode Mode: Mode selection input--it is internally tied to GND through a 30µA current source. RD Mode: When mode is Low. WR-RD Mode: When mode is High. 8 RD
WR-RD Mode
With CS Low, the 3-State data outputs (DB0-DB7) will be activated when RD goes Low. RD can also be used to increase the speed of the converter by reading data prior to the preset internal time out (TI ~ 800ns). If this is done, the data result transferred to output latch is latched after the falling edge of the RD (see Figures 3a and 3b).
RD Mode
With CS Low, the conversion will start with RD going Low; also, RD will enable the 3-State data outputs at the completion of the conversion. RDY going 3-State and INT going Low indicate the completion of the conversion (see Figure 1). 9 INT
WR-RD Mode
INT going Low indicates that the conversion is completed and the data result is in the output latch. INT will go Low ~ 800ns (the preset internal time out, tI) after the rising edge of WR (see Figure 3a); or INT will go Low after the falling edge of RD, if RD goes Low prior to the 800ns time out (see Figure 3b). INT is reset by the rising edge of RD or CS (see Figures 3a and 3b).
August 31, 1994
569
Philips Semiconductors Linear Products
Product specification
8-Bit, high-speed, µP-compatible A/D converter with track/hold function
ADC0820
PIN DESCRIPTION (Continued)
PIN NO SYMBOL DESCRIPTION
RD Mode
INT going Low indicates that the conversion is completed and the data result is in the output latch. INT is reset by the rising edge of RD or CS (see Figure 1). 10 11 12 13 14 15 16 17 18 GND VREF(-) VREF(+) CS DB4 DB5 DB6 DB7 OFL Ground The bottom of resistor ladder, voltage range: GNDVREF(-)VREF(+) The top of resistor ladder, voltage range: VREF(-)VREF(+)VDD. CS must be Low in order for the RD or WR to be recognized by the converter. 3-State data output--Bit 4 3-State data output--Bit 5 3-State data output--Bit 6 3-State data output--Bit 7 (MSB) Overflow output--if the analog input is higher than the VREF(+)- LSB, OFL will be low at the end of conversion. It can be used to cascade 2 or more devices to have more resolution (9, 10-bit). It is always active and never becomes 3-state. No connection Power supply voltage
19 20
NC VDD
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VDD Supply voltage Logic control inputs Voltage at other inputs and output TSTG PD Storage temperature range Maximum power dissipation3 TA=25°C(still-air) N package D package TSOLD TA Lead temperature (soldering, 10sec) Operating ambient temperature range ADC0820CNEN/CNED NOTES: 1. Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. 2. All voltages are measured with respect to GND, unless otherwise specified. 3. Derate above 25°C at the following rates: N package at 13.5mW/°C D package at 11.1mW/°C 1690 1390 300 TMINTATMAX 0 to +70 °C mW mW °C PARAMETER RATING 7 -0.2 to VDD+0.2 -0.2 to VDD+0.2 -65 to +150 UNIT V V V °C
August 31, 1994
570
Philips Semiconductors Linear Products
Product specification
8-Bit, high-speed, µP-compatible A/D converter with track/hold function
ADC0820
DC ELECTRICAL CHARACTERISTICS
RD mode (Pin 7=0), VDD=5V, VREF(+)=5V, and VREF(-)=GND, unless otherwise specified. Limits apply from TMIN to TMAX. SYMBOL Resolution Unadjusted error1 RR E F VREF(+) VREF(-) VIN Reference resistance Input voltage5 Input voltage Input voltage5 Maximum analog input leakage current Power supply sensitivity VIN(1) VIN(0) Logical "1" input voltage Logical "0" input voltage CS=VDD VIN=VDD VIN=GND VDD=5V±5% VDD=5.25V VDD=4.75V CS, WR, RD Mode CS, WR, RD Mode 2.0 3.5 GND GND ADC0820C 1 VREF(-) GND GND-0.1 -3 ±1/16 1.6 PARAMETER TEST CONDITIONS LIMITS Min 8 Typ3 8 Max 8 ±1 4 VDD VREF(+) VDD+0.1 3 ±1/4 VDD VDD 0.8 1.5 1 3 30 -1 2.4 4.5 4.6 4.74 V 200 µA µA UNIT bits LSB k V V V µA LSB V V
VIN(1)=5V; CS, RD IIN(1) IIN(0) Logical "1" input current Logical "0" input current VIN(1)=5V; WR VIN(1)=5V; Mode VIN(0)=0V; CS, RD, WR, Mode VDD=4.75V, IOUT=-360µA; VOUT(1) Logical "1" output voltage DB0-DB7, OFL, INT VDD=4.75V, IOUT=-10µA DB0-DB7, OFL, INT VOUT(0) Logical "0" output voltage VDD=4.75V, IOUT=1.6mA; DB0-DB7, OFL, INT, RDY VOUT=5V; DB0-DB7, RDY IOZ 3-state output current VOUT=0V; DB0-DB7, RDY VOUT=0V, DB0-DB7, OFL ISOURCE ISINK IDD VDD Output source current INT Output sink current Supply current Range VOUT=5V; DB0-DB7, OFL, INT, RDY CS=WR=RD=0 4.5 4.5 7 8 20 6 -3 6 12 0.2
0.4 3
V
µA
mA mA 15 5.5 mA V
August 31, 1994
571
Philips Semiconductors Linear Products
Product specification
8-Bit, high-speed, µP-compatible A/D converter with track/hold function
ADC0820
AC ELECTRICAL CHARACTERISTICS
VDD = 5V, tR = tF = 20ns, VREF(+) = 5V, VREF(-) = 0V, and TA = 25°C, unless otherwise specified. SYMBOL tCRD tACCO tCWR-RD tWR tRD tACC1 PARAMETER Conversion time for RD mode Access time (delay from falling edge of RD to output valid) Conversion time for WR-RD mode Write time Read time Min Max Min TEST CONDITIONS Mode=0, Figure 1 Mode=0, Figure 1 Mode=VDD, tWR=600ns, tRD=600ns; Figures 3a and 3b Mode=VDD, Figures 3a and 3b2 Mode=VDD, Figures 3a and 3b2 Mode=VDD, tRDtI; Figure 3a, CL=15pF CL=100pF tI t1H, t0H tINTL tINTH tINTHWR tRDY tID tRI tP SR CV IN COUT CIN Internal comparison time Three-state control (delay from rising edge of RD to Hi-Z state) Delay from rising edge of WR to falling edge of INT Delay from rising edge of RD to rising edge of INT Delay from rising edge of WR to rising edge of INT Delay from CS to RDY Delay from INT to output valid Delay from RD to INT Delay from end of conversion to next conversion Slew rate, tracking Analog input capacitance Logic output capacitance Logic input capacitance Mode=VDD; Figures 2 and 3a, CL=50pF RL=1k, CL=10pF Mode=VDD, CL=50pF tRD>tI; Figure 3a tRD
Access time (delay from falling edge of RD t o output valid) Access time (delay from falling edge of RD t o output valid)
tACC2
tRD+200 125 175 50 20 200
tI tRD+290 225 270 100 50 290
ns ns ns ns ns ns ns ns V/µs pF pF pF
NOTES: 1. Unadjusted error includes offset, full-scale, and linearity errors. 2. Accuracy may degrade if tWR or tRD is shorter than the minimum value specified. 3. Typical values are at 25°C and represent most likely parametric norm. 4. Guaranteed but not 100% production tested. These limits are not used to calculate outgoing quality levels. 5. VREF and VIN must be applied after VCC has been turned on to prevent possibility of latching.
August 31, 1994
572
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